With the announcements of the first DDR5 memory DIMMs on the one hand and with confirmation from AMD and Intel that their next generation PC processors, Alder Lake and Zen 4, will have DDR5 support. It turns out that DDR5 is going to be the next standard for PC RAM.
Overview of DDR5 memory
Before we talk about the performance breadth of DDR5 bandwidth, we need to explain how it differs from its predecessor, DDR4. The first change being the most obvious of all, which consists in being able to reach the same bandwidth with a much lower consumption. Because the voltage required to reach the same clock speed on the memory interface is lower when going from 1.2 V to 1 V. All combined with a voltage regulator integrated into the DIMM controller, which went from system board to DIMMs. DDR5 voltage and speed setting no longer depends on the motherboard.
Another important change is the use of the so-called On-Die ECC, which should not be confused with the fact that DDR5 is ECC type memory. The difference between ECC On-Die and standard ECC is that it only detects faults if they occur in the same cell or column of memory. This means that DDR5 does not have the classic parity pin of ECC memories where each byte of data transmitted is not 8 bits but 9 bits, of which the ninth bit is parity.
We can not forget Burst Lenght, which has been increased and now allows to feed a cache line from RAM, generally 64 bytes, with a single memory access. Decreased latency and increased bandwidth. It achieves this thanks to its ability to send 2 memory requests of 32 bytes each simultaneously thanks to the fact that DDR5 supports 2 simultaneous access channels per DIMM.
DDR5 memory speed and transfer in MT / s
You will have seen that any RAM memory has in its specifications a datum which puts a certain number followed by MT / s. Which indicates that this is a rate over time, the M is from Mega and refers to 1 million or 10 ^ 6 and the T refers to data transfers. How then is the transfer measured? Well, very simple, the memory has a clock speed called memclk, which is multiplied by one, by two or by four if we are talking about SDR, DDR or QDR memory.
Since DDR5 is a DDR type DDR memory, then the number of transfers per second is that of the memclk multiplied by 2. And there you have to give yourself a general slap on the wrist, since when we talk about DDR5-4800 memory what we usually say is DDR5 at 4800 MHz, but this is wrong, since the memclk is really operating at 2.4 GHz in this case, but performs double the transmissions per clock cycle.
But there is one thing that sets DDR5 memory apart from other DDR memories to date and that is the fact that it supports two memory channels per DIMM. Remember that the number of memory channels refers to the number of simultaneous requests that can be made to the memory module at the same time. Each memory request results in one transfer, and since DDR5 can do two transfers at the same time, things get more confusing.
MT / s do not measure the amount of data sent per send. So despite the fact that DDR5 has gone from 64 bits of data per transfer to 32 bits per DIMM, the number of transfers has increased. So if we compare a DDR4-3200 module with a hypothetical DDR5-3200 module, the first will have a speed of 6400 MT / s, while the second of 12,800 MT / s.
Twice as many memory banks as DDR4
Another change to DDR5 memory related to the support for 2 memory channels for access is the increase in the number of memory banks into which each DDR5 memory chip is subdivided. Since then we have gone from 4 groups of 4 memory banks each to 8 groups also of 4 memory banks each. So internally, a DDR5 DIMM is like having 2 DDR4 DIMMs in terms of memory access.
This is not only advantageous when it comes to accessing the memory through both access channels, and allowing the greatest number of MT / s. Because the advantage of dividing the RAM into a larger number of banks avoids the creation of contention by the memory channels and therefore of latency. Increase the amount of effective and therefore real transfers per cycle that are made. This results in lower latency when accessing data by the CPU and with it higher performance when executing instructions.
Let’s not forget that the MT / s figure given by the manufacturers is a theoretical maximum of performance with the memory transmitting continuously without associated problems of any kind. So, the actual MT / s of a memory is not as advertised, but it will be much more efficient in the case of DDR5 by its nature.
