At the moment, the Zen 4 architecture is just a promise on a slide and not an actual product. It will come, for now, in the form of the upcoming Ryzen 7000 for desktops and EPYC 7004 servers. remained immovable. from the beginning, first Zen.
The Ryzen 7000s won’t be the only processors we’ll see in the coming months with the Zen 4 architecture, but the EPYC 7004s, codenamed Genoa, should also hit the market. Well, we already had an architecture leak last year, which we talked about in a detailed article. Of course, there were always doubts about the accuracy of the leaked documentation, especially since the Zen 4-based CCD chips had not yet entered pre-production and were in the final stages. Design. However, with the confirmation of the L2 cache in Genoa, this information has been confirmed.
This is not the only novelty, since it indirectly confirms that the two processors based on the Zen 4 architecture are at the penultimate stage. Since the information that we are going to comment below corresponds to an engineering sample. Then come the quality ones where the chip is already in its final design, but it’s not yet for mass production, and then obviously the chip that reaches our PCs.
AMD Genoa doubles L2 cache to 1MB
It should be kept in mind that one of the advantages for AMD in the manufacture of its desktop and server processors is that by dividing them by chiplets, it allows them to reuse certain parts. For example, the CCD chiplets used to build the Ryzen 7000 will also be used to build the EPYC 7004 or Genoa. The difference? The number of chiplets and therefore the total number of cores that will be in each processor.
Well, the latest information comes from the Geekbench leak. Although this time it is not a leak of results, but rather a reference to an engineering sample of a processor with 32 cores and 64 execution threads. For that reason alone, we already know it’s not the Ryzen 7000.
What emerges from these specifications is the fact that AMD has doubled the size of the L2 cache per core from 512 KB to 1 MB, which was seen in last summer’s paper. Doubling the size of this level in the hierarchy means that there is a higher chance of finding data there than before and, therefore, the number of results in the search increases.
The increased size of the AMD Genoa L2 cache means that the access time to this level has decreased compared to Zen 3. At this time, we do not know if the rest of the cache levels will be affected. Even if from the outset we tell you not to exclude the implementation of the V-Cache for a potential Genoa-X.
