In order for our readers to understand the significance of AMD’s change in its Zen 4’s integrated memory controller, we need to clarify a basic concept. Access to RAM is not continuous, but the signal is synchronized in a process of different periods in which the signals between the two components, the memory and the processor, are synchronized. Something we explain in detail in an article on how a processor and its RAM communicate.
Thus, when we talk about access latency, we are not talking about communication speed understood as the amount of data transmitted in a unit of time. It is the bandwidth and it is given unrealistically, because there are access windows that prevent communication from being given 100% of the time. The paradox of DDR5 compared to DDR4 is that although it is much faster, it has higher latency, measured in cycles. Does that mean it’s slower? No, due to the fact that DDR5 transmits more data in the same amount of time than DDR4, however, there is a special case
The new DDR5 memory controller for AMD Zen 4
AMD is going to drop the use of DDR4 memory in its Ryzen 7000 based on the Zen 4 architecture, this means a new memory controller compatible with DDR5 which should be able to reach a transfer speed of 5.2 billion transfers per second. For other faster memories, the controller would use the classic method of halving its clock speed, as long as it doesn’t exceed the power consumption limit of that part of the processor and the signal is in sync.
Its biggest novelty? The ability to reduce the clock speed of memory and IMC in exchange for reduced access latency. This, which may seem counterproductive, is essential in certain scenarios where latency is more important than bandwidth. So when it comes to working with DDR5, Zen 4 will start from two different dynamic profiles. One for latency-sensitive applications and one for those requiring bandwidth.
The key is that the more bandwidth you have with memory, the higher the number of requests to RAM, so reducing the bandwidth also reduces the number of requests to RAM. Decreased BMI workload and consequently decreased latency.
Other optimizations we expect in the Ryzen 7000
We expect AMD to have implemented two key performance improvements in the Ryzen 7000 in its next generation of processors. The first of these is the decrease in access cycles to the different cache levels, something in which Intel has had a large advantage in the last generations of processors and one of the weak points to be solved by Lisa Su.
The increased latency of DDR5 widens the distance between CPU and memory even further, so it’s possible that future CPUs will have a new level of cache or adopt V-Cache, which has something to do with more latency, but it increases the cache hit time. In any case, for Zen 4 with V-Cache, we will still have to wait and we are very clear that AMD will implement the second generation, with a much higher capacity.
