AMD Ryzen 7000 and AM5: technical characteristics

In the case of Zen 3, this meant that the AMD turtle surpassed the free Intel. However, the appearance of the Intel Core 12’s Alder Lake architecture once again gave the blue brand the crown as the winner of the moment. And with the Raptor Lake architecture and the Intel Core 13 fast approaching, AMD has no choice but to react with the Ryzen 7000, based on a new architecture: Zen 4.

Basic configuration in the Ryzen 7000

The Zen architecture wraps cores in something AMD calls CCX, which consists of a series of cores with the following characteristics:

• Each core has the private first and second level cache, i.e. the rest of the cores cannot access it.
• The L3 cache is shared and has access to everyone. Additionally, the various cores communicate internally through a network of Infinity Fabric interfaces.
• In Zen and Zen 2, each CCX consisted of 4 cores and their shared L3. In Zen 3 it went from 4 to 8 cores. Zen 4 will have the same type of configuration as Zen 3 and therefore 8 cores per CCX.

When it comes to power, AMD has made a double performance upgrade this time around. First, it increased Boost speeds by over 5 GHz for all processors, which combined with the 15% performance per clock cycle, gives on average 40% more power than the Zen 3 model. compared to the model. However, this means the TDP has gone from 105W to 170W.

Zen 4 architecture will integrate AVX-512 instructions

The first important novelty will be in the support for AVX-512 instructions, which until now was reserved for Intel processors. These instructions, as their name suggests, are 512-bit long SIMD instructions, the longest to date used in an x86 architecture CPU. However, AMD will only support a subset aimed at accelerating AI algorithms. Unofficially, AMD is known to support the following expansions in Ryzen 7000 Zen 4 cores:

• AVX512VL
• AVX512BW
• AVX512CD
• AVX512_IFMA
• AVX512DQ
• AVX512F
• AVX512_VPOPCNTDQ
• AVX512_BITALG
• AVX512_VNNI
• AVX512_VBMI2
• AVX512_VBMI
• AVX512_BF16

Additionally, the implementation of AVX-512 instructions in Zen 4 means that first-level data cache lines and subsequent cache levels have increased the cache line size from 32 to 64 bytes or 512 bits. Which is essential to capture all the data for a single-cycle AVX-512 instruction. This small improvement not only means support for AVX-512 instructions, but the bandwidth of the CPU’s Load/Store units has increased and with it the CPU’s internal bandwidth. Additionally, the fact that Zen 4 can directly load 64 bytes of data means that there is a new AVX-512 unit capable of executing these instructions in a single cycle.

AVX-512 instructions have a limitation, however, namely their high power consumption, which could cause Zen 4 CPUs to run below their usual clock rate when using this type of instruction.

Cache System Changes in Zen 4 Architecture

Since the first AMD Zen, the cache system of AMD processors has remained more or less the same. Except for the last level cache which is shared by all CCD cores, but in the case of Zen 4 there will be changes in the structure of the core cache itself, which you can see in the table next.

The first change to note is in the L2 cache of each corethis will increase the capacity of the 512 KB up to 1 MB of memory, which increases the chances of finding the data in this cache, but instead the L1 and L3 caches remain unchanged in size. That is if, as we mentioned earlier, the size per cache line has increased from 32 bytes to 64 bytes.

There is also changes to TLB or translation-ahead buffers. They are used by the MMU in each processor core to translate virtual addresses into physical addresses. As you can see in the table at the beginning of this section, the translation lookahead buffer of first-level data cache increased from 64 entries to 72 entries. The L2 cache, on the other hand, has gone from the 2048 entries to the 3072 entriesyes Which represents a 50% increase in this aspect and not only the capacity, but also the number of simultaneous accesses.

Interfaces for AMD Ryzen 7000 Peripherals

Not all peripheral interfaces are handled by the motherboard chipset, but some of them are handled by the CPU, as the so-called IOD chip within the multi-piece composite that is the Ryzen 7000 has three functions.

• Intercommunicate the different CCD Chiplets with each other.
• Manage the communication with the memory of the different devices connected internally or externally to the IOD itself.
• Provide connectivity for a number of I/O interfaces found in the IOD, as well as communicate with the motherboard chipset. The subunit in charge of this task is called the Hub IO and it is on this part that we will focus.

Well, if we talk about PCI Express 5.0, we have a total of 32 lanes interface inside the processor. Of which 28 have external connectivity distributed as follows:

• 16 PCI Express 5.0 lanes are for connecting a graphics card. In some models this can be split into 2 connectors of 8 lines each.
• The remaining 8 lines are divided into two four-way channels. At a minimum and per AMD requirements, one must be used for an NVMe PCIe Gen 5 SSD.
• 4 lines that connect directly to the motherboard chipset.
• 4 internal lines, where USB interfaces are connected

Interfaces for Hi-Speed ​​USB Peripherals on Ryzen 7000

Although not officially confirmed by AMD, we know from other sources that the USB hub inside the Ryzen 7000’s IOD is connected to a 4-lane PCI Express 5.0 interface. This means that the bandwidth it can take is 128 Gbps or 16 GB/s bandwidth in total. This figure will be important to understand the configuration.

If we look at the known specifications, we will see how AMD announces that the Ryzen 7000 can have up to 4 video outputs for the integrated GPU. However, this is tricky and to understand it we need to see how the connections are split:

• An eDP connection for an LCD or OLED monitor. Is it possible we’ll see a laptop version of the Ryzen 7000? Who knows, but this could very well be a clue. In any case, many motherboards will come with a standard DisplayPort to HDMI or DisplayPort converter to give video output to the integrated GPU.
• A USB 3.2 Type A 10 Gbit/s connection. This makes it possible to recover the system BIOS from a USB key connected to said port. If not used for this task, it is a conventional data interface.

And what about the rest of the interfaces? Simply with each of them, the designers of the motherboards can choose one of these three scenarios: ?

• Add a USB 3.2 20Gbps Type-A or Type-C port.
• Add two ports: one USB 3.2 10Gbps Type or Type C and one low-speed DisplayPort output.
• 20 Gbps video output, with full support for Display Port 2.0 or HDMI 2.1. The latter via a converter.

We can therefore have up to 4 USB 3.2 ports at 20 Gbps each. Which will occupy 80 Gbps out of the 128 Gbps allocated to the USB controller.

Where do the 14 USB ports come from in the specifications?

One of the conundrums that had us scratching our heads during the Ryzen 7000 showcase at Computex was the statement of “Up to 14 USB ports” in which AMD didn’t tell us where they came from, whether this either chipsets or processor.

Well, after collecting the relevant information, we concluded that the controller of these interfaces is located in the processor. How could we have known? Easy, of the 128 Gbps provided by the 4 additional PCIe lines, we already have 80 Gbps occupied, but we have 48 Gbps left. Well, USB 2.0 ports consume 4.8 Gbps of bandwidth, so 10 of them take up the 48 Gbps we have left. With this, we have already solved the riddle. Which isn’t to say that the X670 chipset doesn’t provide additional ports of this nature.

Of the 14 ports, two of them have specific functions within the system:

• One of them has a direct interface with the TPM 2.0 chip to be able to install Windows 11.
• The second for special functions serves as a hub for SPI/eSPI, GPIO and HD Audio interfaces.

With that, we already have the 14 USB ports that will integrate motherboards for AMD Ryzen 7000 processors. However, we still have PCI Express left.

The new AMD chipset for the AM5 platform?

Once we have described the interfaces of the processor, we must talk about those that the motherboard chipset integrates. For AMD 600 series motherboards, we have two different versions. On the one hand, the B650 composed of a single chip and on the other the X670 platform where there are two chained chips. In this case, only one of them connects to the CPU via its associated 4 PCI Express 5.0 lanes. While the second is subordinate to the first via a PCIe Gen 4 x4 interface that connects the two. Incidentally, the two are twins and are called Promontory 21, abbreviated as PRO21.

The interfaces on each of the chips are:

• 12 PCI Express 4.0 interfaces, 4 of which are used to interconnect the two chips of the X670 and X670E. The B650 therefore has 8 such interfaces. Depending on model
• 4 PCI Express 3.0 interfaces, each of which can act as well as SATA III at 6Gbps. In some cases, these connections can be used to integrate high-speed Ethernet connections.
• 6 x 10Gbps USB 3.2 interfaces per chip. The first two can take the form of a 20 Gbps port. This is the case of the B650. If we talk about the X670 and X670E, then the number of such ports that we can connect is doubled.