In the coming years, the N5 node of Asia’s largest foundry will become the most important manufacturing node in the coming years. Well, through an analysis of one of the chips already made using said manufacturing process, it was discovered that TSMC’s 5nm node density is lower than expected. Is this bad news or a lack of sincerity on your part?
TSMC’s 5nm node and its variants will become the most relevant in the coming years within the PC. Not just because AMD will be using it for future chips like the Ryzen 7000, EPYC Genoa, and RX 7000 GPUs. We also can’t forget that TSMC is also a customer and even Intel, since integrated graphics in Meteor Lake and some Ponte Vecchio HPC graphics components will use it for their crafting. So, one way or another, the major players in the industry are using this manufacturing node in one way or another. Although at present the only chips using this manufacturing process are those of Apple
TSMC’s 5nm node density is lower than advertised
Although this title may seem negative, it has an explanation and that is that from Angstronomics they made an interesting article where they inform us of the reason why TSMC gave the density of its 5nm node incorrectly. By this we mean the number of transistors per area and therefore the complexity of chip construction. The Taiwanese founder officially declares that it is 171 million transistors per square millimeter. However, an exhaustive analysis reveals that this figure is lower and that it is 137.6 million transistors per square millimeter.
They did this by measuring through an electron microscope the size of the transistors used to build the Apple A15 processor in the latest generation iPhone. Lwhich measure 210 nm in cell height and 51 nm in CPP. Well, both values are used comparatively to know the size of a transistor compared to a previous node. Thus, TSMC’s N7 node has values 240nm and 57nm respectivelywhich gives it a density of 90.64 million transistors per square millimeter. In the case of Intel’s 10mm node, recently dubbed Intel 7, we are talking about a figure of 100.33.
If the numbers are making you dizzy, don’t worry. This means that in the same space, chip designers can install up to 51.8% more logic gates on its chips built at 5 nm than those at 7 nm. Which means it’s not a full node hopping. In fact, transistors are not even 5 nm. Since this metric ceased to correspond to reality a long time ago and is more of a marketing tool.
Did TSMC give out false numbers?
No, not really, and that’s because the Taiwanese foundry doesn’t use the metric we talked about in the previous section. What TSMC usually does is adapt an already known chip to the new node to get its metrics. For this they use the design of a Cortex A72, of course since this is a fabless design the founder has all the freedom in the world when it comes to using any type of transistor or another for building the various logic gates that make up the chip.
So, as you can see in the image above these lines, we can deduce where TSMC gets its numbers fromyes And that is that it only refers to the density of logic. So the SRAM or analog parts of the chip are excluded, for example. By the way, we can see how the jump from current nodes to future ones does not translate into a substantial saving in consumption or a significant increase in speed. This partly explains the increased consumption of high-end models of the next generation of graphics cards from NVIDIA and AMD.
In any case, this does not affect any of the foundry partners and the future chips that will be manufactured there. Many of them are already finished and about to be printed on their full-scale wafers.
