For some time now, processors have been integrating other elements inside until they literally become heterogeneous chips that not only literally integrate the processor, but also the memory controller, integrated graphics and other elements. As well as communication with peripherals. Well, that last point is important in understanding why PCI Express 5.0 is so important in the future of the PC.
The problem of physical interfaces
In hardware, we call any interface that communicates a chip with another chip externally, either logic to memory, memory to memory, or logic to logic, a PHY. They are usually located on the periphery of the chip. The problem with them? Whatever crafting node we use, these do not adapt to each new crafting process, so it is necessary to find a way to need simpler interfaces.
One of the most used and at the same time less known parts is what we call a SerDes or Serializer-Deserializer, which consists of an electronic device capable of taking a signal transmitted through a pin or a connection, that is- ie in series, to transmit the same on several pins or connections in parallel. For example, what the motherboard chipset does is concentrate several low-speed interfaces and then concentrate them on a PCI Express connection that is on the other end.
Now if we look at all the existing connectivity for the future we will see how, apart from the use of NVMe SSDs which are directly connected to the processor and the USB4 connections, the rest of the interfaces will see their impact on the connectivity of the board reduced mother. Especially due to the arrival of PCI Express 5.0 and later versions. In other words, it is very likely that we will stop seeing chipsets using 4 PCIe lanes using much less, which will greatly simplify the motherboard.
And what does this have to do with PCI Express 5.0?
The problem is that the chips have become much more expensive per area for a long time, so if you want to keep the prices down, you have to try to make them smaller and that ends up affecting the external interfaces completely. A clear case is in the PCI Express 5.0 lanes of the processor which are intended to communicate with a 5th generation NVMe SSD. Is a 14 GB/s disk really necessary? No, at this point it is not and it is a specification that far exceeds what is needed.
That’s why you can create a SerDES that converts the signal from 4-pin PCI Express 5.0 to 8-pin PCI Express 4.0, which is ideal for having two M.2 drives in your PC. Most users will not use more than two drives in the PC and with this we no longer need the chipset to have to grant connectivity to an additional drive apart from the first one. Everything starts from the processor and thus avoids that laptops are in many cases limited to a single unit.
The other case with motherboard chipsets, which concentrate the majority of low-speed interfaces. These could move from using 2 pins instead of 4, slightly reducing CPU size, however, that won’t be the only component to benefit.
Fewer pins needed for graphics card
The same thing that we explained to you with NVMe SSDs can be done with the graphics card, but this time not for a dual configuration, but for 8 PCI Express 5.0 pins to become 16 of the fourth generation to connect the graphics card. At the moment even the RTX 4090 does not end up suffering from a bottleneck due to the use of said interface and believe us that in the mid-range we will see models much less powerful than said GPU.
As you can see a 16 pin PCI Express 5.0 interface of the CPU is not needed, an 8 pin interface is enough and it will help to reduce chip size or just concentrate said space on the periphery to others things like RAM support with ECC or who knows if more memory channels.
