Taiwan Semiconductor Manufacturing Company (TSMC) just held its 2024 North America Technology Symposium, where it presented its technology roadmap for the future to attendees and investors.
You may rightly be wondering: Okay, but what does this have to do with me, a user of Apple products? Well, TSMC is a chip manufacturing company, and probably the most advanced in the world. They have been Apple’s partner for almost all of its major chips: the A series for iPhone and iPad, the M series for Mac, and more. And Apple is often first in line for TSMC’s new manufacturing processes, paying a premium to be the first customer to use 5nm or 3nm technologies, for example.
Here’s a summary of TSMC’s roadmap and what it could mean for future Apple silicon, and therefore future iPhones, iPads, Macs and more.
What is a nanometer?
Before we talk about TSMC’s future technologies, let’s quickly recall what a “nanometer” is in this context. Technically, it is a billionth of one meter. A human hair has a thickness of between 50,000 and 100,000 nm. Most bacteria are between 1,000 and 10,000 nanometers in size.
In silicon manufacturing process technology, the “nanometric” measurement corresponds to the size of certain features on the chip. Different companies measure different characteristics: This used to be the length between the source and drain parts of a field-effect transistor (FET), but these days different parts are measured by different companies.
The A17 Pro chip was Apple’s first 3nm processor, followed by the M3.
The A17 Pro chip was Apple’s first 3nm processor, followed by the M3.
Apple
The A17 Pro chip was Apple’s first 3nm processor, followed by the M3.
Apple
Apple
In other words, 5nm means that some specific parts of the chip are only 5 nanometers, but TSMC’s 5nm is not the same as Intel’s 5nm, is not the same as Intel’s 5nm. 5nm from Samsung, and so on. A smaller number of nanometers means you can fit more chip logic, cache or other into the same space, which can lead to more powerful chips, lower power consumption, smaller chips that fit into smaller devices, etc.
Think of it a bit like looking at a city in Apple Maps: zooming out makes everything smaller, putting more buildings, streets, and land on the same amount of screen. This is where moving to a smaller nanoscale process equates to more “city” in the same space.
There are many other important aspects of a microprocessor, including how the transistors are isolated, the materials used and much more, but “nano” measurement has remained a way to differentiate one major generation of manufacturing from another .
3nm progression
Apple was the first to offer TSMC’s initial 3nm process, called N3. The company has now refined this with the N3E process, which we believe Apple will use in its most advanced products this fall (A18 and M4). While this may seem important, the main goal of N3E is to make chips more affordable. There are some slight differences in density and performance but this is not a major generational change.
2nm coming next year
The next major change is the move to 2nm, which is expected to happen in 2025. Apple is once again expected to be the first major customer (and perhaps only), so it’s possible that the A19 or other chips (maybe an M5?) this ship in late 2025 will use this process. It all depends on TSMC’s ability to resolve manufacturing issues, yield issues, etc. in time to produce tens of millions of chips with it.
Compared to the N3E process, the N2 process is expected to reduce power consumption by 25-30% (for a chip of the same complexity and frequency) or improve performance by 10-15% for the same power consumption. Chip density (the amount of material that can fit in a single area) is expected to increase by 15 percent.
An interesting change to this generation of chips, besides just being smaller/denser/faster, is what TSMC calls “NanoFlex.” This will allow chip designers to use cells from different chip libraries on the same wafer. Usually, a chip designer should use all the blocks in a “low power”, “high density”, or “high performance” library, depending on the most important needs of the chip. By allowing designs to use different parts from different libraries, chips can refine different areas based on their needs.
For example, Apple might decide that it is very important to make the chip’s video and audio encoders and decoders as small as possible and lay out that part of the chip using the high-density design libraries while using the thrifty libraries in energy for low-power CPU cores and high-performance libraries for high-performance CPU cores.
For chips produced by Apple, the limiting factor tends to be power and heat dissipation. So you can probably expect chips made with the N2 process to contain more “stuff” (cores, cache, larger and more complex video encoders, etc.) to the tune of 15-20%, with speeds of slightly higher clocks and therefore performance. , compared to the previous year’s chips. However, the ability to optimize specific parts of the chip with tools from different chip libraries can potentially pay off in terms of higher “peak” performance or reduced idle power consumption.
The year after the release of N2, TSMC will offer two improved versions of the process: N2P, focused on optimal performance, and N2X, focused on lower voltages and power consumption. It is unclear whether Apple will adopt one for chips arriving in 2026.
A16: We do angstroms now?
The major change after 2nm (N2) is a process TSMC calls A16 (no relation to A16 Bionic). This is a 1.6 nanometer process, but now that things are getting so small, they’re kind of abandoning “nanometers” and moving to “angstroms.” An angstrom is one ten billionth of a meter, or 10 times smaller than a nanometer.
This won’t arrive until the end of 2026, almost certainly too late for Apple to use it that year. We will most likely see chips made with Apple’s A16 process in 2027.
TSMC gave some early estimates for the upcoming N2P process, in which the A16 is expected to improve performance by 8-10% at the same voltage and complexity or reduce power by 15-20% at the same frequency and number of transistors.
The big innovation of the A16 generation will be the supply of energy from the rear, what TSMC calls “Super Power Rail”. This manages a power distribution network at the back of the silicon wafer, connected to the transistors via small tunnels. This improves density and potentially reliability, because power does not need to be routed with all the signal and clock distribution lines on the top side of the chip. Other chipmakers are pursuing similar technologies (Intel’s PowerVia comes to mind) – fundamentally different approaches to the same idea.
TSMC may be a little behind competitors like Intel with this kind of technology, as it’s been pushed back a bit. It was originally planned to debut in the N2P process, and will now be first introduced in A16.
Chips in Apple products that use the A16 process will be able to have even more features (more cores, larger caches) than the N2 process while maintaining the same power profile.
Having chips with more density or a better power profile sooner than others is one of Apple’s great advantages, but the real magic comes from excellent chip design and software development that optimizes the Apple software specifically for the chips they produce.
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