In the Break Breakfast Bytes blog, one of Cadence's (semiconductor) experts in the memory market, he said that while there is still a standard JEDEC DDR5 standard, by 2020 it will be the year of DDR5.
While the new DRAM only appears every 8-10 years, Cadence had its first 7nm DDR5 silicon chips about two years ago, and have been using it ever since.
According to IP DDR, you note that:
- The world's first 7nm DDR5 silicon IP
- The first IP of the 7nm GDDR6 silicon world
- The first IP of the 7nm LPDDR5 silicon of the world
The expert was asked, Marc GreenbergHow to make test chips if standard has not yet appeared and said the following: "Active participation of JEDEC working groups is a good way. We get details on how to improve the common ground. silicon very early. As we get closer to the standard launch, we get more test points to show that our IP will support DDR5 devices that meet this standard »
Marc emphasized that DDR5 is more closely related to complexity than speed. With DDR5 it should have 512 GB of memory for each of the computing stations of the larger sets. With the introduction of DDR4, the 16Gb death is impossible, now it's just a challenge. That's the DDR5 input capacity, but it's expected to hit 24Gb and eventually 32Gb.
The DDR5 is also ideal for mounting, so we can expect to see integrated devices that allow for increased power consumption. One is in 3D and the other one LRDIMM technology, which allows for greater power. LRDIMM (LR stands for "load reduction") is a small part of the market, but may be important for some program designers.
