The hype is starting to grow with these Ryzen 5000 items, we can’t hide it, and we have high hopes of what should be the definitive step for AMD to compete head-to-head with Intel in all areas and markets, without any differences either.
Zen 3 will be the evolution of Zen 2, but this does not mean that development is slow, on the contrary. Most of the problems based on internal slope and RAM will be fixed or minimized, with the exception of subsequent improvements at the end and back end. The first step is confirmed today: structural adjustment and matriculation in between CCD y CCX.
Once again the EPYC with Milan leads the way in Zen 3
The position and design of the Zen 3 will be a very betting series and although the data is falling apart and everything is handled smartly, the first and most important step to increase performance and end of problems is over. to be confirmed by Patrick Shur.
We have to look at where to start, because both the Ryzen 4000 Renoir and the Ryzen 3000 Matisse have monolithic frames according to matric. As we well know, each matrix contains several Maths and within each one we have two CCX inequally.
Each CCX has its own L3 repository, which can be distributed directly within the CCD since we start in two parts. L3 de 16 MB and here is one of the main problems for Zen 2, because according to AMD itself the latency has grown after another architecture to provide statistics between 35 and 40 cycles per second.
Each CCX can be increased to 4 cores, making a total of 8 cores per CCD and from there it continues to add more of these to the main PCB to include all the cores. How will this be handled in Zen 3?
AMD Ryzen 5000: simplify position management and reduce overall latency
The simple one tends to work better than the real complex and as a rule, creates fewer problems. This seems to be the idea that AMD will use in Zen 3, as reported and speculated, this construction work will be edited The 8 cores have an integrated L3 repository for each CCX.
This leaves a completely different view for processors, because by not using the more advanced lithographic process that allows multiple transistors to be used in mm2, AMD can directly output the CCD term and specify CCX directly.
Why? Simply put, they could not increase the number of corals in EPYC or Ryzen, where the cap may have been 64 cores and 128 threads
Although this is unconfirmed and pure speculation, they obviously make sense, but at the same time they are not talking about an important issue: size L3, will AMD keep the same size? There are no rumors of this, but the simplification makes it clear that it may be maintained or reduced, largely due to the dependence on other structural improvements.
Expansion is not possible due to financial costs and the look of the building site, there will have to be very drastic changes to take place and even if it is not excluded, it is possible.
AMD Cezanne teaches paw, tramples A0 with 8 cores
AMD Cezanne [FP6] 🧐
Cores: 8 (4 cores per CCX)
Admission: A0
OPN: 100-000000285-30_Y– Patrick Schur (@patrickschur_) August 20, 2020
The original details on the first laptop processor are here, and although they are minimal, they are just attractive. The chip comes with an OPN code 100-000000285-30_Y
Rumors are new and indicate that AMD will continue with its lapt strategy with its FP6 socket, so we’ll see again. SP3, AM4 and the name FP6 under the same construction parameter. This could mean that the APUs at this time will not have as big a change as the Ryzen 4000, which should mean an early arrival in the market.
AMD Epyc (Milan) ES
OPN: 100-000000114-07_22 / 15_N
Turbo: 2.2 GHz
Base: 1.5 GHzhttps: //t.co/DCH126dnKI– Patrick Schur (@patrickschur_) August 20, 2020
EPYC Milan server follows the same procedure, where the original processor and its OPN code are displayed 100-000000114-07_22 / 15_N, so we are dealing with a CPU with a basic 1.5 GHz clock and a 2.2 GHz Boost of its 64 cables and 128 threads. It has also been reported to be seen in a socket setting designed to make 128 cores and 256 threads, so everything seems to go from strength to AMD power.
Finally, and focused on the desktop, the only thing we know about Vermeer is that CPUs are in the B0 range, so it seems that AMD is not planning on achieving new improvements, especially since we’ve seen this move for months and they live in it. We will see that it ends up leaking before the official launch of these Ryzen 5000, because at this stage they will leave us with hype until the first day of the shoot.
