At the helm will be an Intel which will try to come back with all its strength and resources and which is in a process of change whose effects we do not know. AMD cannot stand idly by and has not done so in recent years with Zen architectures. Luckily for Zen 4, we can get a rough idea of what we’re going to see in 2022, but let’s not forget that we don’t have all the information yet.
AMD Zen3 + before AMD Zen 4?
One of the rumors circulating in recent weeks is that AMD has ported the AMD Zen 3 from the 7nm process to the “6nm” process, both of TSMC, I put it in quotes because it is really a node that the foundry Taiwanese created to take advantage of part of the infrastructure for the 7nm UVV. The particularity of said node? It gives up to 18% more density than the 7nm node, but we don’t know how AMD is going to use it.
The last time AMD used an upgraded version of a node was when it used Global Foundries’ 12nm node for the creation of Zen +, but we’re not sure if we’ll see any changes in it. internal architecture. in any way, a slight rise in the CPI. But what we do know is that AMD and Global Foundries are ending their contract this year and it is very possible that we will see a new IO Die, which means AMD will be completely renewing the Northbridge and Southbridge since. the launch of the Ryzen. 3000.
Among the changes of the new IO Die or IOD for Zen 3+, there is the support of DDR5 memory, which is not an evolution of DDR4 and therefore requires a new design in terms of memory access and support for PCI.Express 5.0, but we do not know if like Intel it will come with CXL 1.0 support.
AMD Ryzen 7000, the possible trade name for Zen 4-based processors
If we take into account the launch of Zen3 + with a new IO Die accompanying its chiplets, they could appear at the end of 2021, so by a simple rule of three it is clear that we will see them as Ryzen 6000, therefore Zen- les 4-based processors would be those based on Zen 4.
Crisscrossing the release dates, we have the end of 2020 for Ryzen 5000, 2021 for Ryzen 6000 based on Zen 3+ and 2022 for Ryzen 7000 and Zen 4, which is when it will be released under TSMC’s 5nm node.
Most likely, the Ryzen 7000 will be desktop-only in a chipset configuration in conjunction with a 7nm IO Die, while the monolithic laptop version will not appear until 2023, when the 5nm node is mature enough for large SoCs.
What changes can we expect at the chiplet level in Zen 4?
First, we’ll see a hybrid core setup to increase the IPC, all based on combining a kernel for complex instructions with a kernel optimized for simple instructions into one, sharing only the hardware of capturing instructions, all as a measure to increase CPI. It doesn’t look like Zen 3+ is going to be fully optimized for DDR5, but the change in memory type presents an opportunity for AMD to redo the entire instruction capture mechanism, especially if dual channel by DIMM is leveraged. DDR5.
The other big change is the increase in the number of cores per CCX, which would go from 8 cores to a larger number, a number that at the moment we do not know, but we must remember Lisa Su’s comments on AMD augmentation plans. the number of cores in their AMD EPYCs, which obviously translates into an increase in the number of cores per chip.
It is possible that increasing the number of cores will modify the cache hierarchy, adding an L4 cache that would be located in the Northbridge or a new IOD, which could well be a last level cache or a replacement Victim Cache in this task on current L3 cache. All this would simplify the L3 cache in the chiplets in order to be able to place a greater number of cores.
New type of interconnection between chips and IOD for Zen 4?
AMD takes advantage of the same technologies for its processors and GPUs, so it wouldn’t be surprising if AMD decides to use the new type of interconnect for 2.5DIC that we saw in the patent for its chipset-based GPUs, which would make a lot of sense. In fact, AMD is planning to replace the Infinity Fabric interfaces externally with new ones.
If L4 cache is confirmed for Zen 4, chip communication to IO Die will increase, reason is that L3 cache could be made private by Zen 4 core and it would be necessary to communicate them all one by one. by one instead of groups of 4 or 8, it is at this stage that the development of the X3D interface to replace the Infinity Fabric.
AMD is not going to create two separate interfaces for external communication between the chips in a 2.5DIC configuration, whether it is to communicate the CPU chips or the GPU chips.
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