Communication between CPU and RAM, how is it?

In this article We are not going to tell you which type of RAM is the best. or nor the specifications of each, but a processor communicates with it to be able to execute the programs.

The reason why we use external memory that is why the number of transistors needed to store information would not fit in the space of a processorThis is why it is necessary to use RAM memories external to the processor to store the instructions and the data to be executed.

Why does a processor need to communicate with RAM?

The step in which the CPU takes the next instruction to execute from RAM is called “Fetch” and is one of the three steps that make up an instruction cycle: Fetch-Decode-Execute, of which we will only talk about the first one in this article, while the other two will be left for another time because RAM memory does not intervene in them, except to rewrite the result.

Each processor has a series of registers connected to each other that are used to capture the next instruction, they are:

1. Program counter: The PC points to the next memory row where the next processor instruction is located. Its value is incremented by 1 each time a complete instruction cycle is completed or when a jump instruction changes the value of the program counter.
2. Memory address register: The MAR copies the contents of the PC and sends it to the RAM through the address pins of the CPU, which are wired with the address pins of the RAM.
3. Memory data register: If the instruction is read, then the RAM will transmit via its data bus the contents of the memory address to which the MAR pointed.
4. Instruction register: The instruction is copied into the instruction register, from where the control unit will decrypt it to know how to execute the instruction.

What is DRAM memory?

he type of memory used for RAMboth as system RAM and video RAM or VRAM, is the DRAM or 1T-DRAM memory. In this type of memory, every bit is stored in the ccombination product of a capacitor and a transistor, instead of doing it in multiple transistors like SRAM, hence the name 1T-DRAM.

All RAM memories currently used in the PC: DDR4, GDDR6, HBM2e, LPDDR4, etc. These are DRAM type memories, while the internal memories of processors, register caches and scratchpads, are SRAM type.

This combination of a capacitor and a transistor is called bitcell, When the capacitor of the bit cell is charged then it is interpreted that the information the bit cell contains is a 1, when it is not loaded then it is interpreted as a 0.

The bitcells are organized in a matrix where the addressing pins are used to access them as follows:

• The first half of the bits select the row we want to access
• The second half of the addressing bits contains the column we want to access,

For this, there is a binary decoder between the matrix of bitcells and the addressing bus which makes it possible to select the appropriate bitcell.

Contact pins for communication with RAM

To access the RAM, the CPU uses a series of pins that allow you to access and even edit the contents of it. To do this, you must first locate where the data is located or where we want to manipulate it and then pass it in a specific direction. Two different types of pins are used for this.

• Pin addressing: Normally marked from A0 through AN, where N is the number of pins and is equal to the number of addressing bits, which is always 2 ^ N.
• Data pins: This is where data is transmitted to and from RAM memory.
• Enable writing: If the spindle is active, the data transfer is done to the memory, in writing, on the other hand, if it is not active, it is done to the processor, in reading.

If our system has multiple RAM memory chips, the first few bits of the addressing are used to select which memory chips we want to access in the DIMM memory module. There have also been cases where the address and data pins are the same. This is because addressing and data access do not occur simultaneously.

But to understand how addressing works more precisely, we need to review a basic electronic element, the binary decoder.

The binary decoder and its role in communication with RAM

The binary decoder is a very common electronic part, it consists in that from an input of n bits an input is selected among 2 ^ n different possibilities. It is built by placing n NOT gates on 2 ^ n AND gates.

In RAM memory, addressing is transmitted in two cycles: first the row to be accessed is sent and then the column, instead of simultaneously.

The reason is a very simple explanation: Imagine you have a processor with 16 bits of addressing connected to a single RAM memory chip. If the binary decoder was 16 bits, 16 NOT gates and 65536 AND gates would be needed. In contrast, an 8-bit binary decoder has 8 NOT gates and 256 AND gates, which are much easier to implement.

This is the reason why addressing to RAM is done in two steps.

Memory banks

Data in RAM are not stored successively, but in different banks within the same chip, each of the banks contains an array of bitcells, but if we want to transmit eg n bits of data, we will need n arrays of binary cells where each of them is connected to a pin of the data bus.

The use of several banks, on the same memory chip, allows you to select multiple bits at the same time with a single memory access, because all banks share addressing. So if we have 8 memory banks, selecting a specific bit cell will eventually cause data to be transmitted to and from all 8 memory banks at the same time.

The standard size of banks in RAMs is 8 bits, so maximum addressing memory is always counted as 2 ^ n bytes. In fact, the 16, 32, 64 bit, etc. What they do is transmit data from several successive memory addresses starting with the first.

Communication between RAM and CPU

Communication between the CPU and RAM depends on its correct execution, i.e. the correct data is sent, in the right direction and in the right memory bank. Therefore, all RAM memory has a window of opportunity, which is the time during which the different operations can be performed, these must be performed at specific times and following this process:

1. Select the (Addressing) column
2. Select the line (addressing)
3. Data transmission.

For this a series of special pins are used, one of which we have already seen and this is Write Enable but the other two are as follows:

• Column access strobe: This pin is activated when we tell the RAM we are indicating the column we want to access.
• Line access strobe: : This pin is activated when we indicate to the RAM memory that we indicate the row that we want to access.

The two operations can be summarized as follows:

• The read operation is very simple, for this you must have the WE pin inactive, to indicate that the data goes from the RAM to the processor, indicate the row then the column so that the information flows to the processor from the RAM memory .
• The write operation is somewhat different, for this the WE pin must be active, but the data is not transmitted after the selection of the data column but once the row is selected and simultaneously with the selection of the column where it is the data.

With this, you can already get a rough idea of ​​how communication works between a processor and its RAM.