The increase in the capacity of their partners to continue in the coming years will only be compared to what they gave at the beginning of this century. And it is fast in terms of the highest quality lithographic processes that will deliver, without any improvement in the design itself, a very significant increase in the number of calls.
Therefore, the amount of data to be handled with the function will be very high, so RAM should be compatible, as well as BMI. Later we don't know how both Intel and AMD will handle it and most of all on a scale, but we can be sure of what SK Hynix has prepared for this new change.
High speed, high capacity and low power: this is how Hunnix looks at the DDR5
In addition to the above upgrades, SK Hynix will introduce, at the JEDEC level, a new development that will confirm the details: ECC. As they noted, they were working on their DDR5-6400 modules, which will reach the market with a simple configuration of 16 GB.
The difference with current modules about performance is not only the difference in pure speed they will receive, but also the number of banks the new DDR5 is able to withstand in comparison to the current DDR4.
<img src = "data: image / svg + xml,% 3Csvg xmlns = 'http: //www.w3.org/2000/svg' viewBox = '0 0 3 2'% 3E% 3C / svg% 3E" class = "aligncenter size-full wp-image-398879" data-src = "https://igamesnews.com/app/uploads-igamesnews.com/2020/04/SK_hynix_DDR5_Advantages.jpg" alt = "SK_hynix_DDR5_Advantages" width = "1000" height = "1148" data-srcset = "https://igamesnews.com/app/uploads-igamesnews.com/2020/04/SK_hynix_DDR5_Advantages.jpg 1000w, https://igamesnews.com/ application / download -igamesnews.com / 2020/04 / SK_hynix_DDR5_Advantages-261×300.jpg 261w, https://igamesnews.com/app/uploads-igamesnews.com/2020/04/SK_hynix_DDR5_Adentialities-892×10.jp: hard
And that we are from 16 banks with four groups of banks going to 32 and 8. respectively, that is, the length of the crack is doubled and thus discontinuous.
This also has some effects that DDR4 cannot achieve, and it is a bank update when used, that is, until now the system was not allowed to use other banks during one update, which will do with DDR5 and This improves memory accessibility.
Effective, safe and cheap?
As we mentioned, SK Hynix is seeing the DDR5 in a much broader perspective, and that is that it will come with its new 10 nm lithographic process in the second generation, which means a further reduction in production costs. In addition, in this case we have to add two important and practical benefits to the design of DDR5 as memory: ECC and ECS.
Error correction and debugging will cover this type of memory with each list, so error and feature detection are expected to be the most important to reduce the final cost before each module leaves the factory, which would greatly reduce the number of error modules and consequently RMAs.
In addition, high speed modules will introduce a new design and feature called DFE, which will remove the jitter and signal noise when these speeds are active, such as the invention DDR5-8400. Attempts to maintain the stability and security of information by increasing the speed per pin.
The total value will be enhanced, because we will achieve 64 GB module each, where no matter where everyone will come by 1.1V voltage. We think this number will change as the speed increases or its length decreases. As for the latter, latitude, nothing has been specified yet, but as usual it will be a series of parameters that should be taken into account.
