With the advent of manufacturing technology Extreme Ultra Violet (EUV), the complexity of the multi-model techniques developed in the previous technology nodes can now be applied with the finest resolution provided by EUV. This, combined with other more technical improvements, can lead to a decrease in the size of transistors, allowing us to continue with the future of semiconductors and, now finally, we have reached the 2 nanometer era.
The first 2nm chip comes from IBM, how does it work?
Today’s announcement claims that IBM’s 2nm development will improve performance by 45% with the same power, or 75% efficiency with the same performance compared to modern 7nm chips. IBM would like to point out that it was the first institution to demonstrate 7nm in 2015 and 5nm in 2017, the latter having moved from FinFET technologies to nanosheet technologies that allow further customization of the voltage characteristics of individual transistors. .
IBM says its process technology can place 50 billion transistors on a single chip the size of a fingernail (about 150 square millimeters), by placing the density of the transistors on this chip to 333 million transistors per square millimeter (MTr / mm2).
As you can see, the different functions have different official names with a variety of densities. It should be noted that these density numbers are often listed as peak densities, for transistor libraries where area is the primary matrix of concern rather than frequency scaling; Often times, the fastest parts of a processor are half as dense as these numbers due to thermal and power issues.
As for the move to GAA / Nanosheet transistors, although IBM doesn’t explicitly state so, the pictures show that this new 2nm processor uses a three-cell GAA design. Samsung already uses GAA at 3nm, while TSMC is hoping to achieve its own 2nm for this. Rather, it is believed that Intel will somehow introduce it into its 5nm process.
IBM’s 3-cell GAA uses a cell height of around 75nm, a cell width of around 40nm, and the individual nanofilts are 5nm high, separated from each other by 5nm. The polygonal pitch of the grid is 44 nm and the length of the grid is 12 nm. IBM claims that its design is the first to use lower dielectric isolation channels, allowing a gate length of 12nm, and that its internal spacers are a second generation dry process design that helps enable the development of these nanosheets. . This is complemented by the first use of the EUV model in the FEOL parts of the process, enabling EUV at all stages of the design.
Our readers may wonder why IBM is the first to have a 2nm chip and not Samsung or TSMC, which you hear most about today. IBM continues to own one of the world’s leading semiconductor technology research centers, and although they do not have their own foundries, they develop their own products in collaboration with others. IBM has sold its manufacturing facilities to GlobalFoundries With a 10-year partnership commitment in 2014, IBM is also currently working with Samsung itself and in fact recently announced a partnership with Intel.
No details were provided on the first 2nm test chip, although at this point it’s probably just a simplified SRAM test circuit with electrical logic. Images of the 12-inch slices show a variety of different light diffractions, likely pointing to a variety of test cases to assert the technology’s viability. IBM says the test design uses a multi-Vt scheme for high performance and high efficiency application demonstrations.
The chip was designed and manufactured at IBM’s research facilities in Albany, USA, where they have a clean room of no more and no less than 30,500 square meters. The purpose of this facility is to exploit IBM’s vast portfolio of patents and licenses precisely to conduct collaborations with its partners.