IBM’s announcement of the 2nm process is a demonstration that the hardware will continue to evolve over the next 5 years as it always has and continuously, but in turn, said announcement generates a series of unknowns as the number of nanometers for a long period of time corresponds more to marketing than to physical reality.
This week we saw the announcement of IBM’s new manufacturing node. What can we expect from this node and what will be the leap from the nodes currently used for the manufacture of various chips and memories?
Comparison of IBM 2nm node with current nodes
The chip sample that was fabricated with IBM’s 2nm node has a density of 333 million transistors per square millimeter. Keep in mind that the density of transistors depends on what is built with them, and memory is much denser than logic, so not all areas of the processor made by IBM in its experimental 2nm node have such a density. In any case, measuring the density from what the SRAM occupies in each node is normal in these cases.
The news is important in the face of a situation in which Moore’s Law seems to be slowing more and more and with the general feeling that a node is going to be reached only in terms of development costs, deployment or physical limitations. not flea to be scaled further. .
In reality, we are facing a knot so we have to wait until 2024 or 2025 at least for it to be put on the market.
Are they really at 2nm?
TSMC’s 7nm node density is 96.5 million transistors per square millimeter. It must be taken into account that the density of transistors increases quadratically with the decrease in their size. For example, to double the density of a node, just multiply the size by 0.7. For example, if we take the one at 7nm, we only have to multiply that size by 0.7, which gives us a node of 4.9 at 5nm.
But are we really looking at a 2nm node? To know the density that a hypothetical future node would have, it suffices to do the following calculation:
Scale factor of the node to convert to = (1 / known node) ^ 2
Then we just have to do the following:
Density of transistors of the new node = Density of transistors of the known node / Scale factor of the node to which it is planned to convert.
With the first formula, we get a scale factor of 0.08, indicating that a hypothetical 2nm “real” node would have a density of almost 1200 million transistors per square millimeter. Almost four times more than that announced by IBM, but on top of that we must add that TSMC’s 7nm is not really exactly 7nm, but a much lower density and therefore a much higher node in real nanometers.
How does it compare to the rest of the existing nodes?
The reason it is called the 2nm node is because its density is higher than the 3nm nodes advertised by Samsung and TSMC. In Samsung’s case, the advertised density for its 3nm node is 180 million per square millimeter, while TSMC’s 3nm process has an advertised density of 315 million.
The reason IBM calls its node “2nm” is simply because its specs are much higher than those of TSMC and Samsung. Now we will see the arguments for this.
2nm IBM node speed and power consumption
Another important point is how the processors evolve in speed and consumption, that is, if we make an existing chip under the new node. How fast would it reach or how would consumption be reduced? The two at the same time cannot be, so the two digits are given separately.
A processor manufactured under TSMC’s 7nm node, under IBM’s 2nm node would go 45% faster in clock speed for the same consumption. Whereas if we kept the clock speed, the power consumption would drop to 75%.
Clock speed, however, has a trick, as it always searches for the exact point on the voltage and clock speed curve that is highest. The same goes for the consumer, where it looks like IBM got a better node in terms of the energy consumed.
The IBM 2nm node receives its name in the highest energy efficiency, and this is due to the use of what is called HNS or Horizontal Nanosheets, a technology that Intel will use in its 5nm node, which will compete with your to your face at the 3nm nodes of Samsung and TSMC. We know Samsung will adopt them in the future, but we don’t know if TSMC will or if they will go with another solution.
The joint venture between IBM and Intel
Yes, this statement may sound very shocking to you, but you have to keep in mind that IBM, unlike Intel, does not have its own foundries, but designs chips and, most importantly, invests a lot in the design. new chip manufacturing. nodes that it licenses to third parties. So it’s a different business model from TSMC, Samsung and Intel.
That is, IBM designed the standards for a new manufacturing node and then created a sample chip, which is a design that brings together all the common elements of a contemporary processor design and which was recreated using an experimental version of its 2nm node.
IBM has worked with GLOBAL FOUNDRIES on a regular basis, but they gave up racing altogether and didn’t reach 7nm. IBM’s partner in this case is therefore Intel and we may be looking at the specifications of a future Intel node.
Additionally, there is a possibility that we are faced with the specs of Intel’s 5nm node, with which they would stand up to TSMC and Samsung’s 3nm nodes that we discussed earlier in this article.
IBM’s 2nm post under review, what improvements does it bring to CPUs and GPUs? first appeared on HardZone.
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