While we have all congratulated and marveled at Zen's chiplet build, where version after version has seen significant improvements in performance, the fact is that according to the IPC it seems that there is a limit to Intel's seeming ignorance of its monolithic architecture.
On the other hand, Intel is in a position to have trouble keeping up with the number of cores compared to AMD. This situation will produce something unprecedented in this field where two officials will join their cause: TSMC y DoD (United States Department of Defense).
Chiplets are the future, but not at this price
AMD has hit the key, but has a very important problem in the near future: CPU designs are becoming more complex and this leaves some The cost of R&D continues to increase.
If we add to this the fact that the values contained in their processors, it is not surprising that the equation starts to fail sooner rather than later. Not surprisingly, we have already discussed that AMD will have to raise prices on its new building and products, and that they are leaving the cost-benefit path as a company.
This doesn't seem like enough in some years from now and in conjunction with Intel, TSMC and DoD, the idea is to present a presentation with various industrial levels allowing homogeneity in the processor and at the same time not limiting the R&D of each company.
Though AMD has put you in the meeting, but the costs themselves and Intel carry over to Foveros about the stars, which along with more advanced lithographic processes such as those designed by the TSMC are encouraging inflation that in the short term will not even be taken by companies.
2.5D package, 3D, build methods and translators
With this in mind, the future goes through a combination of processes as we've been seeing for the past year with technologies like CXL. It will not be enough for each of the opponents to move freely in their designs, not if they want to survive the expense.
The key phrase here is "commercial standing«, Which will not be easy to do because of individual company projects. But the demands on the industry and the future partnerships they ultimately have to accelerate the launch of their products in the marketplace, reduce the cost of chiplet integration and simplify testing for each of them. for a time a separate package
This will require a series of common standards that describe the features in which the industry will operate and that is where all those teams will work collaboratively to define and thus enable future CPUs. The goal is that any client can combine and align different chiplets and link them using a death-to-death link system standard, that is, using a A standard translator.
This should be allowed in designs 2,5D such as the one from AMD or 3D just like Intel & # 39; s, so it won't be easy to come up with a new standard build that allows the use of all predefined features.
Normal positioning will avoid expensive testing and error detection
One of the key points in the structure of surfaces, chiplets and substrates is the fact that the test detects defects in wafers and chips they should be cheap, is easy to accomplish so you should spend less time on it.
The issue of the current system is precisely to get rid of invalid layers due to various problems in recording or filtering. Keep in mind that stack recommended by AMD and Intel is required a large number of layers, so getting a troublesome issue early allows chips to be removed before the installation step, which is expensive for details like TSV.
Therefore, one of the first things that Intel, AMD, TSMC and DoD will have to do is measure the cost of testing, the cost of malfunctioning the wafers and fault detection in order to carry the technology it has designed. high volume production.
So the big four are facing a huge challenge and with their only interaction will the future CPUs come up, because their vulnerabilities depend on this configuration. This of course does not mean that monolithic CPUs were discontinued, but as Intel said a little over a year ago, costs also began to be a problem.
To this we must extend the leave we will see in less than 10 years lithographic processes. Monolithic CPUs will then recognize this problem in front of the screen: if transistors are not reduced, more faces of each computer will be needed to enter their maximum number, a matter we know exactly where it ends and the atomic limit will act as a theater.
