The word chiplet seemed ridiculous a few years ago, but today it has become a safe future. In particular because it leads to a reduction in costs and breaks with the limitations of the monolithic system in terms of cost and size. It is therefore quite normal that the industry ends up developing a universal connector between chiplets which it has called UCIe.
With the increase in processor production costs, the adoption of chiplets to build with several chips what was previously done with only one is a reality. At the PC level, each of the major hardware designers has already launched or has just launched an architecture built in this way. It was therefore necessary sooner or later to agree on the creation of a universal connector that would allow chiplets of different brands to communicate with each other.
Industry Launches Universal Chiplet Interconnect Express
The world’s three largest foundries (TSMC, Intel and Samsung) along with a series of technology partners such as ARM, Google, Meta, Microsoft and Qualcomm have launched a new standard. Which consists of a communication interface that they named UCIe or Universal Chiplet Interconnect Express. Which is used to communicate with each other the different chips mounted on a common substrate. That is, a processor that, instead of being made up of a single piece, is made up of several that are interconnected with each other.
The new UCIe standardIt is based on PCI Express with Compute Express Link and among other things, it will allow the creation of chiplets made up of parts from a single manufacturer, otherwise we will be able to see architectures where not only elements with different manufacturing processes are combined, but also from different suppliers. This completely changes the current paradigm, since until now solutions of this type have tended to focus on solutions from the same manufacturer because there is no universal standard to date.
In any case, the existence of the new standard is not something that should surprise us, especially since collaborations between foundries for the creation of different parts of the same CPU, GPU or APU will be increasingly more common. We have the perfect example of this in the collaborations between Intel and TSMC for future projects of the former.
What are the characteristics of USI?
At the moment the standard is not final, but they have published a series of initial specifications in the form of version 1.0 of the standard. Which comes with two different types of interconnects. Let’s not forget that these are vertical interconnections of each of the chiplets with respect to the interposer, which is the communication substrate on which they are mounted to transmit the signal and therefore the data. This allows them to reach bandwidths greater than one terabyte per second
Translated into something that can be understood in conventional language, it must be taken into account that the transfer speed to traditional RAM is currently generally between 6 and 8 pJ/bit on average, depending on the type of memory used. Low power is one of the keys to this type of interconnects, designed to transmit large amounts of bandwidth between the different components. This is essential for processors composed of dozens of cores in the server market, as well as for GPUs composed of chiplets.
