To understand the solution, we must first be aware of the problem, understand it and know what are the limits that will mark us, so in this case we will start there, with the problems of today’s transistors. A transistor is the smallest electrical unit that can be fabricated for an electronic component, an electrical element as such that is made up of semiconductors and recorded by incredibly advanced scanners using wavelength on mirrors.
It is basically a switch interconnected between dozens of silicon layers (as a rule) of very small size and which has an extremely clear function: to modify the flow of current passing through it, to give it up or to cut it. Each cut or step represents either a zero or a one in binary and with time, what has been achieved is to improve it by allowing more speed in the change of state, more or less energy for said change and more or less efficiency when leaving the current pass.
We are approaching the edge of transistor technology
As we have already thought, each transistor has a series of designs which vary depending on the manufacturer. Intel has its vision, TSMC the same and Samsung more or less, so although all of them are more or less copied in the advancements, the implementation and improvements are different.
Ten years ago, Intel introduced the FinFET transistor, which was chosen by all manufacturers, but this design is coming to an end for several reasons. With this type of transistor, we had a flexible design of the same, usually wide, where multiple gates passed through it, allowing manufacturers to better control power management, welding, and building materials, as well as continue to reduce its size in nanometers.
The main problem we have is simple: it cannot be reduced much more in size, because we have limited longitudinal space, and the gates of each transistor cannot join together without losing electrons. To this must be added that the distance between them is so small that welding and interconnection require new materials and extremely expensive alloys, some still experimental, which guarantee the passage of energy and do not trigger the price. .
Who is the solution? A new type of transistor that not only allows more layers that conduct current, improve control, soldering and efficiency, but also reduce the distance between transistors in Angstroms (unit of molecular and atomic measurement).
RibbonFET, Intel’s solution to the new limit of lithography
If you can’t keep shrinking the space and controlling all the settings without triggering the cost, all that’s left is to explore a new path. This new path in the form of a new architecture for the transistor is called GAA or also known as Gate-All-Around. From there the concept is divided into three aspects or even 4 (it is not entirely clear):
- TSMC GAAFET.
- Samsung MBCFET.
- Intelligence RibbonFET.
- Global Foundries is in limbo with rumors, but nothing concrete.
What is happen ing here? Well, as happened with FinFET, GAA is going to have several variations all based on the same concept of transistor. We have already talked about Samsung MBCFET, GAAFET has not yet been exhibited as such although it will arrive with the company’s 2nm, so after Intel’s presentation in its Architecture Day 2021 and after revealing some additional details, we will know the bet of the giant blue: RibbonFET.
The concept is simple, but difficult to implement. They take a transistor of flexible width which will be reduced with each lithographic jump and which allows multiple layers, now called nanosheets, dry sheets or fins by the industry, to be connected vertically in the transistor instead of being horizontally. What is achieved? Well, first of all, greatly reduce the width of the transistor, allow more nanosheets on a smaller surface and above all, a single Gate which will control all the energy of the cell.
The electrostatics have improved tremendously as Intel showed in their official presentation, where we only have to see the sizes of the Pitch Gate and Gate Stack. It goes from 6 nm x 50 nm to 12 nm x 7 nm and with more control and better welded nanosheets.
A variable nanosheet design according to the needs of the transistor
Apparently and as we have seen in various documents since Intel talked about this new type of transistor, it seems that the blue giant can collect a varying number of nanosheets per transistor.
This detail is important, because as Intel descends lithography based on better EUV scanners, it will either be able to keep the same number or remove the ones it needs to optimize each gate. The documents show 2 to 5, but in the last datasheet the round number appears to be 4. More fins / nanosheets require more steps to create the transistor, so it increases the cost of each chip, so Intel will start. maybe with a number through them until you have improved the engraving and production control, materials and welds that allow you to eliminate a certain number of nanosheets and reduce costs without compromising the stability, speed or efficiency of the transistors.
This will logically depend on the height of the gate and with it how many sheets we can fit into it, because now instead of being surrounded by three sites like it happened in FinFET, each end is completely surrounded by the gate. , which means one side is optimal, but the other makes it difficult to reduce the height between the sheets.
When will Intel RibbonFET be implemented in its chips? According to the company itself in 2024, surely at the end of that same year if all goes well, although if the navigation goes smoothly, we could see it by the middle of that same year. In any case, it will be your 20A lithographic process that will include it and compete GAAFET from TSMC and MBCFET from Samsung. Intel is so confident it will make a difference that it has already said it will lead the semiconductor industry and its technology again in 2025 – no doubt a statement of intent.
