So far the only Intel-confirmed benchmark of multi-chip processors, we have them in their Intel Xe HP GPUs where we’ve seen several pre-production samples by their creators, but we didn’t have any multi-design benchmarks. -chips in a processor so far, but that Sometimes the information is not from Intel itself.
An Intel Xeon made up of chips
Photos have been leaked of what could be the Intel Xeon Scalable Processor under the architecture Sapphire RapidsThese show an LGA processor with the “Intel Confidential” seal, so we are in a pre-production prototype.
Pre-production prototypes are used to test and complete final tweaks before final production, aside from the fact that they run at a lower clock speed than the commercial model, in this case at 2 GHz.
How do we know it could be Sapphire Rapids? Due to the fact that we already know what the old Intel Xeon is on the roadmap and what stands out is that it doesn’t use a monolithic chip but is made up of two symmetrical chips.
Does Intel adopt chips like AMD?
AMD’s design is to completely separate the integrated Northbridge and Southbridge in the form of IOD (i.e.) while what the multi-core processor with its caches is in different chips, at the square Intel’s design appears to be made up of two symmetrical chips.
This MCM configuration by Intel reminds us instead of the dual-core version of Pentium 4, the Pentium D, which consisted of two symmetrical Pentium 4 chips mounted on the same interposer.
Why would Intel look for a chipset configuration?
How the bigger a chip the fewer chips come out per slice, not only that, but the larger a chip, the more potential errors per zone increases and the number of good chips coming out of a wafer is reduced.
On some manufacturing nodes when reaching a certain height with regard to chip size, wafer performance, the number of good tokens per tranche.
Architects adapt the size of the chips they design to the efficiency of the node that will be used for their manufacture, of course, if we are talking about processors as complex as an Intel Xeon or an AMD EPYC, it is how much you have to divide the chip into smaller ones with it in order to increase productivity and reduce costs.
The architecture of Sapphire Rapids
The cores used in Sapphire Rapids will be the Intel Golden Cove, who will have integrated the Advanced Matrix Extensions (AMX) as good as Instruction sets and units AVX512_BF16 and AVX512_VP2INTERSECT, which are intended for use in data centers, the target market for Intel Xeon Scalable processors.
In addition, the new processor will use a DDR5 memory controller, who integrated the Data flow accelerator o DSAoutside a bus PCIe 5.0 of 32 GT / s with the support of CXL 1.1 protocol, to improve connectivity between the CPU and the various accelerators.
The processor will be manufactured with thl 10 nm SuperFin nodo from Intel itself
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