eXtreme Memory Profile or XMP has been with us since 2007 and in this third version with hindsight and after 14 years, it is normal that the blue giant launches a new revision with novelties. Because? For the changes that DDR5 implies compared to DDR4. We will not go into this subject since we have already covered it in extension, but if there is something to say about XMP 3.0 it is that it is exclusive to DDR5 as such.
The term Profile of its name comes to the fore to explain the first of the points that Intel has given to manufacturers, since as we know this technology is based on the recognition of a series of configuration tables that each manufacturer integrates to taste by model, chip, and memory version for the IMC to recognize and apply these settings through the firmware.
What’s new in Intel XMP 3.0
These tables include speeds in MHz, clocks and primary, secondary and tertiary access times which are logically faster in some cases or slower in others, but which in all cases increase the general performance of the memory. and with it the system. In the first version called by its own name, XMP, Intel managed to include the inclusion of reading a profile in memory plus that of the JEDEC (technically it is a profile, but they are counted as two)
XMP 2.0 raised the bar to two reading profiles, where builders could establish whether they wanted two different values and tables, personalizing the user experience and prioritizing different performance (three reals including JEDEC). With XMP 3.0, manufacturers can now have two or three profiles to include, with the option of selecting two customized by the user.
SPD update
One of the key points of the XMP profile is precisely the specification SPD o Presence detection in series. This has caused a lot of headaches for manufacturers and users, mainly because it can be written from EEPROM and therefore get corrupted. Some programs can do this and of course this creates crashes in the memory controller as it cannot read values from the XMP properly and the memory is unusable until a new blink occurs correctly.
Now and with XMP 3.0 we will have two updatable profiles which helps that if one gets corrupted the other can let the memory run, its SPD can be extracted and later it can be flashed. module by module, repairing memory as if nothing had been passed.
CRC checksum
Oddly enough and already explained, why DDR4 modules with XMP 2.0 do not have CRC? It’s not exactly like that and logically there is a why. The CRC as such was added in its Write version in the JEDEC standard for DDR4, but the cyclic redundancy code has a problem: high bandwidth consumption. The data shows the consumption of 25% of total system write
This is no longer a problem with DDR5, since in addition to including the PMIC in the memory itself, in the module physically speaking, the speeds are and will be monstrous compared to DDR4, especially if we have a double bandwidth that integrates this type of memory. Therefore, Intel with XMP 3.0 incorporates the wanted CRC checksum which will protect the data and integrity of the SPD as well as the CPU memory controller.
Bigger space increase for XMP 3.0
One of the key aspects and already understand everything we have said about the new XMP 3.0 is that, logically, we need more space to house it all. For this reason, Intel has gone from 78 bytes per module from XMP 1.0 to 102 from XMP 2.0 and is now raising it to 384 control bytes
This is what makes it possible to select predefined memory profiles like SPD from the BIOS / UEFI of the motherboard. The question that arises then is the behavior of the BMI of the new Alder Lake and Meteor Lake processors (a significant frequency jump is to be expected) with the different speeds that we will see from the manufacturers and the chips. .
Are we going to see XMP 3.0 profiles above 6000 MHz? Can the IMC of the CPUs withstand them without overflowing the voltage and with it consumption and degradation? At the moment, we know that there are brands working on profiles for DDR5-7000, so it looks like either these new memories and chips manage to scale much faster than CPUs and their IMCs, or it means the Download potential and support / endurance of the integrated memory controllers is greater than one might think.
It should be borne in mind that although XMP 3.0 achieves very high speeds in some modules, it is the IMC that determines whether it is able to withstand said speed and its voltage, which is logically independent of that of the RAM itself.
That said and clarified, we can only say that Intel has made a very big step forward, the most important since the launch of XMP in 2007 and as such, it is now AMD which will have to adapt its technology and IMC to these new requirements with Zen.Quatre.
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