The artificial intelligence market is occupied by designer brands of accelerators, such as NVIDIA GPUs. Intel wants the AI server market not to depend on purchasing an external accelerator with its upcoming Xeons, even if they need to add HBM memory to do so.
Specifications of the following Intel Xeon
Intel has released a table in which we can see the specs for its Xeon which will be released after the recent Ice Lake-SP, which is called Sapphire Rapids, but which was called EAGLE STREAM instead of Xeon by Intel itself.
Its specifications as you can see in the table are as follows:
- The number of cores per processor will drop from 40 of the current Xeon cores to 56 Golden Cove cores, the same that will be used at Alder Lake for processors in laptop and desktop processors later this year.
- Unlike current Xeons, Intel will adopt a chip-based design for the first time. Which will be composed of 4 symmetrical processors of 14 cores each.
- Configurations of 2, 4 and 8 processor sockets, on the other hand the TDP went from 270 W to 350 W.
- The RAM will not be DDR4 but DDR5 with 8 memory channels. The maximum supported speed will be DDR5-4800.
- 80 PCI Express 5.0 lanes, compared to the current Xeon’s 64 PCI Express 4.0 lanes, also with CXL support.
- UPI 2.0, the Ultraprocessor Interconnect now uses 4 lines and its speed has increased to 16 GT / s.
- Deep Learning improvements, with the addition of AMX units,
But what really stands out is the possibility of using HBM memory, in particular each processor has a 4096-bit HBM2 interface, with which it can be connected to 4 HBM2e batteries with a total capacity of 64 GB and 1TB / S bandwidth, which translates to monstrous bandwidth for what a processor is.
Why do you need Intel Xeon HBM memory?
A few months ago when we told you about the support for HBM memory, especially HBM2E, in the next generation Xeon, we mentioned that an HBM memory stack supports up to 8 memory channels, just as we can connect the processor to 8 channels DDR4 or DDR5 we can do it to 8 channels of HBM memory.
What we weren’t expecting was a setup using a 4096-bit HBM interface, which translates to an impressive 1TB / s bandwidth, which is an exaggeration for what a processor is, l ‘explanation? The addition of Intel AMX units, which is a systolic matrix similar to those used in the Tensor cores of NVIDIA GPUs and Google TPUs. All of these cores require large amounts of bandwidth to operate.
This means that Intel will stop using inefficient AVX-512 units, both in terms of consumption and architecture, to bet on a type of hardware already proven in the face of all that surrounds artificial intelligence in its next generation Xeon. We don’t know if he would include it in Lake Alder, given the bandwidth required by AI algorithms.
