Artificial intelligence requires us to accelerate the development of different technologies to improve their capabilities. One of those that would be accelerated is the PCIe 7.0 interface, of which we have already seen a prototype from the company Cadence System. We were able to see this PCIe 7.0 prototype this already allows speeds of 128 GT/s during PCI-SIG DevCon 2024.
You are probably wondering what GT/s or Gigatransfers per second are. This information is important in PCIe interfaces, which are a serial bus with an integrated data clock. Data transmissions are encrypted.
PCIe 5.0 offers 32 GT/s with 128b/130b encoding. We need to send 128 bits of data, 130 bit transfer with encryption is required. If we multiply the Gigatransfers by the coding (32 GT/x * [128b/130b]) we will have a speed of 31.5 GB/s.
PCIe 7.0 interface overview
You should know that the new version of the PCIe data bus is in the middle of the development phase. What was shown is a preliminary prototype, there is still a long way to go before it is fully developed.
The PCI-SIG DevCon 2024 event, we can say, was a great success for the Cadence company thanks to its prototype. At the event, they presented their first IP solution for the new data transfer interface. Event attendees were able to see a demonstration of the TX and RX capabilities of PCIe Gen 7 with a speed of 128 GT/s. To achieve this, a linear optical connector was used, achieving low latency and no synchronization.
The company highlights that it achieved a steady transfer of pre-FEC BER throughout the two-day event. There was no downtime, which is a significant milestone and leaves plenty of room for improvement with this new technology.
Quite interestingly, the PEM4 histogram of the receiver showed good linearity and margin. We are talking about the first demonstration of transfer between TX and RX of 128 GT/s. Of course, this required commercial optical connectors, unlike last year’s solution which required special communications media.
A great technical advance has been made to be able to offer these capabilities in a technology in the development phase. But that’s not the only thing they showed during the event, they performed different demonstrations on PCIe such as:
- PCIe 7.0 with optical connection.
- PCIe 7.0 electrical.
- Interoperability of consecutive PCIe 6.0 RP/EP interfaces.
- PCIe 6.0 communication protocol in FLIT mode with Lecroy Exerciser.
- PCIe 6.0 communication protocol in FLIT mode.
- PCIe 6.0 JTOL data interface with Anritsu and Tektronix equipment.
- PCIe 6.0 communication protocol with Viavi Protocol Analyzer.
- Demonstrating PCIe 6.0 system-level interoperability with the PCIe Gen5 platform.
A collection of demonstrations from Cadence, an industry leader in the development of professional PCIe-based solutions. Although the progress in the development of PCIe 7 stands out above all, it also highlights the capabilities of PCIe 6. This latter interface, most likely, will begin to be deployed next year in professional sectors such as data centers and AI systems.
