The chip manufacturing processes that our hardware uses are usually expressed as a number followed by nanometers. But what does this term indicate today? Well, objectively nothing and that is why nanometers are a lie, because it has become a marketing term by all factories or foundries of transformers. Whether we are talking about Intel, TSMC, Samsung and even the Chinese minimum wage.
The nanometer lie today
Until the late 90s it was referring to the length of the logic gates used to build the various chips or semiconductors, but from the 250nm node a more aggressive position began to be taken regarding the length. doors. . For example, the 250nm node used logic gates with a length of 200nm instead of 250nm, and the trend was upward with the 180nm node, the length used was 130nm.
This forced a change in the definition of what the metric was when defining a manufacturing node, which became the half step, which for several generations coincided in length with the manufacturing node. But today they don’t match anymore and nanometers have become a marketing term to inform us that a manufacturing node used by a factory or a foundry to make all kinds of semiconductors, or chips, is better than the previous one. .
For example, TSMC’s so-called 20nm process has the same density as TSMC’s 16nm FinFet process also, but the trade name of the latter case has been used to talk about improvements through the use of FinFet transistors. We can also talk about the comparison between 10nm node from Intel and 7nm from TSMC.
How would lithographs be scaled to nanometers?
Moore’s Law tells us that chips increase the density of their transistors every certain number of years, we must take into account that it was invented in the sixties where the manufacturing node corresponded to the length of the gates. logic, which are distributed in a matrix throughout the chip.
This is why reducing the length of each logic gate by 30% results in halving the size of a chip with the same internal organization. Decreasing the length of an object by 30% means reducing it by 0.7 times and 0.72 they are 0.49 times and therefore double the density, since you place the same quality of transistors in half of the surface.
What does this have to do with the current situation? It’s simple, for example changing from a 16nm FinFet process to a 7nm process, if the classic measurement is used it would be a four-fold increase in density, but instead it is promoted with twice the density. Which is further proof that when large foundries talk about a certain number of nanometers, they are not mentioning a technical specification, but a marketing term.
