What AMD and TSMC are doing is very impressive, perhaps not at Intel’s level with Foveros (for now) but what is certain is that even if technologically they are not up to the mark for the moment. , in performance they will position themselves as leaders (except surprise with Alder Lake-S).
AMD Zen 3 3D Caché, a 15% performance jump in gaming
The numbers slipped in by Lisa Su give this number as an average result, but now we know the oddities of why. And won’t adding an extra vertical chip as an increased cache, as has been speculated, be a level 4 cache, or in other words, technically it won’t be the Victim Caché? typical.
Everything is much simpler in theory, but in practice the numbers are overwhelming and we explain ourselves.
What AMD achieves with this vertical cache is that Windows and CCDs see the added chip as “transparent”, that is, there is no physical change to the software or hardware in it. their mode of operation between cores and IOD.
What you will see is one more L3 cache block, which will be manufactured at 7nm by TSMC and measure 6 x 6mm (36mm2) connected directly to the CCD caches via TSV. And here is the magic, because in the case of the 5950X which was shown at the time with this technology we are talking about no less than 192 MB of L3 in total for the existing 64 of the original model that we can currently buy.
TSV dizzying figures, at Intel’s level
Each CPU will have more than 2 TB / s of bandwidth thanks to this new cache and its TSV connections, which we now know are made by bumps in what is called “Dark side”, Each TSV is connected from the FEOL of each CCD to the Bonding surface by Nails in copper. They are in direct contact with the BEOL of this new cache, which allows the exchange of information from substrates and caches.
To give us an idea of the complexity of all this vertical stacking, we calculate that for each L3 partition of 4 MB that has a CCD there is 3000 TSV with a size that includes between the 6.1 µm and 17.3 µm thick.
For the squaring of the circle, more stratospheric data is given, because in the SMU they are calculated 56 TSV and 14 more in the so-called test area.
What do we have in total in the new 5950X? Well a huge 24070 TSV to connect the two substrates, while, as we said before, the area of the new AMD 3D cache is only 36 mm2. These figures are undoubtedly staggering and which will allow AMD to beat Intel, at least temporarily.
