Therefore, we already know that PCI-Express is nothing more than an interconnect interface; is developed by the PCI-GISwhose existence could be broadly defined as a consortium of manufacturers and designers who agree to create an interface with certain requirements, so that their devices can work in tandem and, precisely, communicate with each other according to these requirements.
This interface has been developed since 2003 to the present day, and started as an evolution of the AGP and PCI standards. The PCIe 1.0 version, introduced in 2003, was quite simple but already represented great improvements over AGP and PCI, since it had a data transfer capacity of 2.5 GT/s (GigaTransfers per second) and 250 MB /s for each data path.
If we compare this with the current PCIe 5.0, capable of handling 32 GT/s and 3,938 MB/s via the data path, things have certainly changed a lot. But wait, now PCI-Express 6.0 is coming to improve the present again.
PCI-Express 6.0: technical specifications
Data speed | 64 GT/s (double PCIe 5.0) |
---|---|
Format | PAM-4 with Flow Control Unit (FLIT) encoding |
channel range | SNR supply reduced by 9 dB |
backward compatibility | Yeah |
bit error rate | 0.000001 |
Duplex | Complete |
As usual whenever a new generation of PCI-Express interface comes out, 6.0 offers literally double the bandwidth of PCIe 5.0, or 32 GT/s. You probably know that when we talk about PCIe sockets on PC motherboards, we mean it with a multiplier, such as PCIe 5.0 x16, which is currently used by graphics cards. Indeed, for us to understand each other, they have several “paths” that work in parallel, so the bandwidth can be multiplied.
Thus, one can find PCIe interfaces of 1, 4, 8 and 16 lanes sending data in parallel, and with PCIe 6.0 this results in a data flow of up to 256 GB/s (whereas in SSDs at M.2 format is 64 GB/s maximum). Be careful, because we are talking about the additional bandwidth in both directions, i.e. reading and writing simultaneously.
backward compatibility
The PCI Express interface has always been backward compatible with previous versions of the protocol, meaning you can plug a PCI Express 1.0 card into a PCI Express 6.0 slot and it will work. It’s called backward compatibilityand this is thanks to the fact that the pin layout has always been the same in all versions of the interface.
Be careful, as this is also a double-edged sword, because to increase bandwidth you cannot place additional pins, and therefore you must increase the clock speed at which the interface operates. In other words, data pumps per second to transmit data are faster to generate higher throughput, which may have disadvantages such as higher power consumption and greater heat generation.
The problem with PCI Express 6.0? As we increase the clock speed of an interface it becomes more and more unstable and after six generations they had to make changes due to the high speed at which the interface traditionally operates. The problem is that to transmit 256 Gb/s over a Full Duplex interface, which allows 1 bit for each direction to be transmitted simultaneously, the interface speed must go up to 128 GHz and at those speeds the integrity signal is seriously compromised. engaged.
This has forced a series of measures to be adopted to make the transition to PCI Express 6.0 possible, starting with the coding, which is the next thing we will explain.
PAM4 encoding in PCIe 6.0
How does an external or internal interface of a chip know if the value is a 1 or a 0 (remember that we are in binary system)? In fact it’s simple: depending on the voltage at which the information is transmitted. Binary systems are based on the use of two voltages with sufficient distance between them so that the voltage drop or rise does not confuse the receiver of the signal.
What does this have to do with PCI Express 6.0? As we cannot increase the bandwidth because the signal is distorted, nor the number of pins because then we would not have backward compatibility, we have to find an alternative solution. In the end, they found it using the encoding called PAM4 (Pulse Amplitude Modulation 4), which we have already seen in GDDR6X memories.
This type of encoding is not based on two values like the binary system, but on a total of four different possible voltage values for each of the pins. In this way, we can encode the values 00, 01, 10 and 11 on each pin: four values in total, instead of the two classic values which would be 0 or 1.
This solution avoids having to increase bandwidth and pins, but it tells us that in PCI Express 7.0 this will no longer be possible from conventional methods. We can see the use of photonics and optical interfaces, but with the improvements of PCI Express 6.0 fresh out of the oven, better bear with its successor.
PCI-Express 6.0 no longer communicates… all the same
The move to PAM4 also changed the way the PCI Express 6.0 interface sends its packets, despite being compatible with previous generations, which used the previous system called PAM2 or NRZ. The reality is that the PAM4 format does not support the old packet system and hence the communication protocol has changed due to this.
We mentioned earlier that the high speed of PCI-Express 6.0 can cause instability, and with it errors, which is why it was also necessary to integrate a new error correction protocol called Forward Error Correction
To remedy this, the PCI Express 6.0 standard uses a type of packet called FLY. A packet is nothing more than a set of bits with a specific destination. The sending latency of each FLIT? Depends on the number of lanes on the interface, but each packet has a latency of only 2ns on a 16-lane PCI Express 6.0, but up to 32ns on a single-lane interface.
FEC only works with fixed sizes, and that’s why FLIT has a size of 256 bytes per transmission. Each packet or TLP can have a size ranging from 0 bytes to 4096 bytes and therefore each packet can consist of multiple FLITS.
And this is where the cyclic redundancy check comes in, known as CRC in English for its acronym “Cyclic Redundancy Check”. It is a code error correction system commonly used in storage devices and digital networks, and has been incorporated into the PCI-Express 6.0 standard to verify that data transmitted end-to-end retains their integrity and not a single bit was changed in the process.
This is achieved with a series of polynomial calculations performed by a series of specialized units which are included with the interface. This makes sense with the huge amount of data to be transmitted and represents a saving, especially for future SSD manufacturers who will not need to add this feature to their drives as it is standard on the interface itself. even.
Low Power Mode in PCI-Express 6.0
Finally, it is interesting to note that PCI-Express 6.0 adds a new state of low consumption baptized as L0P. This mode allows the interface to reduce its power consumption when the data rate sent is below its maximum. It does this by being able to change the clock speed that the connected device needs for specific times when the data to be transmitted is less bulky.
This mechanism is closely related to the new technologies introduced in the sixth version of PCIe 6, so it can only be used with devices compatible with this generation of interface (in other words, for LoP low-power mode, it there is no backwards compatibility, it will only work with devices that natively support PCIe 6.0).
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