At its simplest level, Moore’s Law refers to the doubling of transistors in a chip with each generation of the manufacturing process. Over the years this exponential increase in density of transistors has remained remarkably constant, but two things have changed along the way: the way we get these increases in density and the benefits to be gained at the product level.
The future of Moore’s Law according to Robert Chau
Whether it’s higher frequencies and lower power consumption or more features built into a chip, Moore’s Law has stood the test of time and has evolved to meet the demands of each generation. technology, from mainframes to mobile phones. This evolution will continue as we enter a new era of unlimited data and artificial intelligence.
What innovations will Moore’s Law bring about over the next decade? I think they can be classified collectively into two pretty broad areas: monolithic scaling and system scaling. The monolithic scale can be called the “classic” Moore’s Law scale, with an emphasis on reducing the size of transistors and operating voltages while increasing the performance of each transistor. System-wide improvements are the gains that help us incorporate new types of heterogeneous processors through advancements in high-bandwidth chip-to-chip interconnect technologies, packaging and chips.
Intel is investing heavily in research to support both vectors; At the 2019 annual meeting of the world’s leading semiconductor process technology pilots, MEI in San Francisco, Intel engineers presented nearly twenty papers demonstrating groundbreaking work securing a bright future for Moore’s Law for generations to come. . The following is a high-level summary of these exciting technology options.
Monolithic scale: a new dimension
Current generation Intel processors are based on a transistor structure known as FinFET, in which the gate surrounds the fin-shaped channel on three sides. As Intel’s compute nodes advanced, they made the ailerons taller but narrower, reducing the number of fins needed to achieve a certain level of performance.
While FinFET still has a long way to go, at some point in the near future the industry will switch to a new type of transistor architecture: Full opening FET (GAA), in which the gate surrounds the channel on all sides. There are several potential implementations for GAAFET, from thin nanowires to wide nanoribbons. What they have in common is the ability to pack more high performance transistors in a given area, thus reducing the width of the standard cells that our designers use to build new processors.
In addition to this new transistor architecture, another way to drive the scaling of the cell area is to vertically stack transistor devices. Modern semiconductors are built from complementary pairs of positively and negatively charged transistors called NMOS and PMOS. The height of a standard cell can be greatly reduced by monolithic stacking an NMOS device on top of a PMOS device, or vice versa. This can be achieved by stacking FinFET, GAAFET or even a combination of both.
Monolithic stacking of transistor devices not only offers improved density, but is an exciting way to integrate multiple materials onto a single silicon substrate, providing dramatically improved performance and opening the door to whole new product classes with unique functionality.
System scaling: beyond the transistor
Continuing to lead the future of Moore’s Law requires incorporating improvements into all aspects of the manufacturing process, not just at the transistor level. For decades, many in the industry have viewed packaging as just a final manufacturing step, the place where we make the electrical connections between the processor and the motherboard. However, this has changed drastically in recent years and is now a crux in the entire manufacturing process.
Ten years ago, SoC integration focused on implementing CPU and I / O functionality on the same chip as a high performance CPU. In the future, advanced packaging technologies will be used to link different types of processors together, but without forcing them to share a single build material or process node.
This type of decay may seem, at least at first, to be the antithesis of what Moore’s Law is supposed to achieve, but the performance and density improvements achieved by matching each type of processor to its own design implementation and to its own logic of Low tuning transistors often outweigh the inconvenience caused by breaking down a monolithic die into smaller chips. In fact, in his original 1965 article, Moore stated that “it may be more economical to build large systems from smaller functions that are packaged and interconnected separately.”
Intel has already implemented technologies such as EMIB (Embedded Multi-die Interconnect Bridge) and Foveros to connect two- and three-dimensional chiplets, such as placing HBM memory between CPUI and CPU (as in Kaby Lake-G, with EMIB), or to connect the 10nm Compute Matrix used in Intel Lakefield processors face to face with the 22nm I / O Matrix directly below. They also plan to combine Foveros and EMIB in a technology called Co-EMIB, in which multiple 3D Foveros chips are connected through EMIB, allowing Intel to build chips much larger than the grid size for any processor. monolithic and scaled chip designs in a much larger way than before.
Intel is already looking, in fact, beyond Co-EMIB, for a new standard called “Omnidirectional Interconnection” (ODI). One of the problems with stacking chips on top of each other using existing methods such as silicon vias is that the amount of energy that can be pushed through these small wires is very limited. ODI uses much thicker pathways for power delivery, while providing the same capabilities as Foveros when implemented for face-to-face 3D linking.
ODI can be used to connect chips in a wide variety of configurations, including scenarios where one die is partially “ buried ” and acts as a bridge between two others, or even between two slightly overlapping dies, with ODI used between them for a few. thicker power pillars, allowing chips to get much closer.
The possibility of integrating 3D stacks of processors presents another method of improving the density of silicon which is completely decoupled from the “classic” concept exclusively focused on Moore’s law transistors. Traditional monolithic scaling will continue at 7nm with the introduction of EUV, then 5nm and well beyond, but this is not the only area where Intel is hoping to face further improvements. from generation to generation in terms of density and performance.
The improvements that will lead to the future scaling of Moore’s Law at Intel are not driven solely by reductions in process nodes or improvements in lithography, but by the collaboration between several engineering teams involved in different parts of the design process. Here, Intel’s unique status as an Embedded Device Manufacturer (IDM) is an advantage, as Intel manufactures its own products and there is close collaboration between the design teams and the engineers who make the parts. Thus, we have the possibility of modifying an architecture to better suit the capabilities of a process node, or of adjusting a node to match the capabilities that we want to offer in a given architecture.
It cannot be denied that we face significant challenges in the industry, but the future of Moore’s Law will be anything but a slow decline towards obsolescence. Expanding how we deliver improvements on a generational scale has broadened the options for implementing them, and Intel has never been more optimistic than now about the long-term health of Moore’s Law. .
