For processors and chips to evolve, a foundation is needed to determine the performance and capabilities of the new technologies they will host. Even if an engineer has in mind how to approach them for years to come, how to do it is the really complicated step. We have seen how the industry is turning to chiplets, but although they are a reality that is gradually taking over the market, one of the key technologies and concepts is little known. How did we get here?
InFO and its two variants PoP and oS are the key to evolution
Before we dive into the technology itself, we need to know what InFO is. As such, InFO stands for Integrated Fan-Out, which is often referred to in the industry as wafer-level packaging, which would result in arriving as a technology platform for systems integration.
That is, a method of adding subsystems or components to the chips already present in the wafer itself. A clear example is HBM inside any chip in vertical format (not horizontal because GPUs that need a substrate or interposer, don’t confuse them) although any type of DRAM would work as well. , for example.
In order to integrate a subsystem or a component at the slice level, it will be necessary to use RDL (redistribution layer) high density and also technology TIV (via InFO via) to make the interconnections between the two layers without loss of performance. The process consists of cutting the chips out of a silicon wafer and then placing them very precisely on a thin “reconstituted” or carrier wafer, which is then molded. The redistribution layer is created, then solder balls are formed on top, like in a chip-scale package at the wafer level. After that, the new chip formed wafer is baked so that the compound is hardened and ready for production.
Variants involve being able to design 2D or 3D chips
As we have seen, InF O has two variations which, depending on the chip design and its complexity, can be used for its creation on the wafer. We are talking about PoP and oS, where each has its own peculiarities and for the moment and despite the fact that they are used from 16 nm, neither ends up imposing itself on the other as a clear dominant.
InFO_PoP is the first Fan-Out package for the industry in the 3D wafer concept. It is most used when integrating components such as matrices, DRAM or substrates interposed for several layers. It has the particularity of using finer welds, which gives it a finer final profile and better electrical and thermal performance due to the absence of organic substrate.
In contrast, InFO_oS needs a substrate to be able to take shape, where the normal height will be around 2 micrometers. The advantage is that by including the substrate, more chips can be interconnected with it and that doesn’t depend on something as individualized as the PoP method. Giving I / O or input measurements is complicated, because every company has its own and every node needs to resize them, but in any case, we are still talking about micrometers.
It was this technology that allowed Intel and TSMC to defeat Moore’s Law for a few more years, albeit evolving multi-wafer systems.
InFO-L / LSI, the pinnacle of system scalability
A new technique within InFO should be nearing completion to be mass-produced from 2022. We are talking about InFO-L or InFO_LSIPreferably, a silicon interconnect layer is integrated between the substrate and the chips, which improves aspects such as signal integrity and even voltages or temperature, as they require lower values.
The problem is that the chips must be designed with a lower thickness so as not to increase the total height of the die too much, thermally limiting the dissipation between layers. This is interesting when it comes to GPU or CPU cores plus HBM in one of its variants.
Adding height limits the maximum tolerable values, as we’ve seen for example in the i9-9900K or the Radeon VII, so it’s not something to really despise. New chips coming out of the factory have to do this, so it will be interesting to see how much they increase over the original substrate.
