The idea of apilar varios chips e interconectarlos in vertical 3DIC, en el mercado ya la hemos visto en forma de las memoria HBM, pero el hecho de unificar memoria y lógica in a diseño 3DIC o incluso varias capas de chips basados en la lógica es mucho more difficult. While in the case of HBM memory we have seen designs of up to 4 stacked chips, in the case of logic + memory or logic + logic we have only seen two-chip compositions.
Stack up to 4 layers of chips in a 3DIC design
Although with the HBM memory found in high performance graphics cards, it already uses a 4-layer configuration, all memory, The American Institute of Microelectronics, IMC, has taken a technological step forward that allows up to 4 layers of chips or semiconductors to be stacked to form a single chip in a four-layer 3DIC configuration.
The approach proposed by the IME is based on the association of a pair of wafers face to face, so that the two are connected on the same side, which we will call A. To then connect the other two chips at the ends but connected the back side or B. Once this procedure is done, channels are created for the paths through the silicon to pass through the four chips, thus allowing the interconnection between the four chips that make up the 3DIC composition.
The problem with a chip stack is the thermal suffocation between the different chips, which becomes more complex as the stack increases in number of components. It is for this reason that for example the HBM 3 memory has not yet seen the light of day due to the internal debate on whether to increase the number of chips at a lower speed and with it the width of the bus or the speed of the bus itself. In both approaches, the challenge is the same, the temperature.
Will it be adopted by Intel and / or AMD?
Well, we don’t know, at the moment Intel and AMD’s bet seems to be for 2.5DIC systems in which multiple chips are connected in a common interposer, some of them are regular chips and the others are 3DICs. At the moment, both AMD and Intel do not plan to use paths through silicon, but what are called Silicon Bridges or Silicon Bridges, at least to connect the various components of the MCM on the interposer.
Another different thing is the vertical composition, adding up to 4 tokens makes for a less interesting concept. What would consist in separating, like the Lakefield, the Chipset or the Southbridge from the rest of the CPU on the one hand, on the other hand it would be based on the addition of additional last level cache in one or the two remaining layers. Increasing top-level cache with 3DIC is critical for the performance of certain applications that require both bandwidth and memory capacity. Where the solution is usually to use complex HBM memory systems, such as future Intel Sapphire Rapids will be transported.
