There is no doubt that Zen 4 is going to be a very big change in performance by AMD, all supported by the adoption of TSMC’s 5nm node for the design and construction of a much more complex processor and which allows for achieve a higher CPI than its predecessors.
One of the key points to achieve superior performance is the design of the cache, not only its speed, but also the amount of information it can hold and the concurrent accesses it supports. A higher number of instructions resolved per cycle also results in a higher number of accesses and an increase in their size.
Changes to the Zen 4-core L2 cache
Thanks to a series of leaks, details of the next generation of AMD processors were known in advance. This time it was Zen 4’s L2 cache, which as you can see in the table above would have gone from 0.5MB or 512KB per core to 1MB, doubling its capacity.
In Zen architectures, the L2 cache is private for each of the cores, L3 being used as LLC for each group. From the information that has been leaked, we know that Zen 4 will continue with the 8-core configuration around the L3, each with their corresponding L1 and L2 caches, so doubling the size of the L2 cache on newer processors serves to improve. CPI by increasing the chances that the necessary data and instructions do not have to go to L3, and therefore any blow at this level is resolved much sooner.
AMD has a big challenge to overcome
Well, really little, although we have to assume that its CPI increase is going to be way above the 15% granted by the V-Cache version of Zen 3+. The revamped data speaks of a 19% increase in the CPI, which would be too low a jump considering the improved iteration of its predecessor. In any case, the completion of the design of the Zen 4 cores could not have been completed and the team led by Mike Clark still have time to improve, moreover, we believe that the launch of Zen 3 improved (Zen 3+ supposedly) It is a way of giving time to the realization of Zen 4.
At the moment AMD has not filtered out the amount of L3 that Zen 4 will have, it makes us think that they are planning to launch the fourth generation Zen with vertical cache from the first moment, which would mean an improvement in performance compared to to the original design. The trade-off is that it will make the production more expensive. Is this why AMD will launch its Zen 3 with V-Cache with the intention of testing the market?
With an Intel that has put the batteries in with Alder Lake-S and that has already completed the Meteor Lake design for 2023, it’s up to AMD to make Zen 4 as competitive as possible. They must be more ambitious than with Zen 3 where they were limited to TSMC’s 7nm node.
