Customers are in control. This is a saying that we have definitely heard more than once and in the chip field there is no difference. The findings provide the node with a series of yields and prices at each price, confirming delivery and depending on all this the customer decides whether to purchase.
This is not news like this, but it should be considered that it is the customer who will decide the type of pattern to apply to the aforementioned wafers, so the technical jump in which the find is available is important to ensure the sale.
Making multiple patterns in one place will be a temporary problem, so EUV will reduce the sector's demand. The solution will come from the same technology that has already been cut: EUV NA.
Technology is going one step further and they want to avoid patterns with EUV NA
The most obvious question is undoubtedly the most important, what is EUV NA? Before answering it we must put ourselves in a position. From 28 nm, the reduction of the lithographic process had some problems eliminating the recording.
The solution to these problems is patterns, of which a large number of them allow achieving exact recording of transistors and architectural maps, but this imposes greater complexity and higher costs on the surface of each pattern used.
Not surprisingly, Intel is charging each CPU as gold today for the complexity of these projects, while AMD by taking advantage of the lithographic process and TSMC can provide large numbers of transistors in a single pattern, currently making Taiwanese economists more economically viable.
Therefore, there are only two alternatives available from the observed 28 nm: increasing the number of patterns or increasing the so-called NA (Counting Numbers). The NA is connected to the lens of the recording machine and allows for an increased amount of exposure, more insight into its manufacture and therefore it is possible to record these transistors at low nanometers.
I mean when the NA is high, a low lithographic process is achieved.
2023 key date for a new lithography problem
We are only two and a half years away from alarms from all the founders in the world. So far the key is held by ASML, which offers its NXE: 3400C with EUV to several of its competitors, Intel included, but this is only the first step to be taken to avoid cost escalation.
Whether AMD, Intel or NVIDIA, to name the three giants in the industry, wants to use multiple recordings under EUV, but the fact that ASML & # 39; s 0.33 NA of 7nm EUV is far enough to extend life processes lithographic and their complexity other than many ways.
The latest connection that can be made with this technology is the EUn's 5nm TSMC and this could be double standard if the manufacturer's design is really complex, but the cost will start to rise in the sky.
For this reason, ASML is working hard to introduce its own DATE: 5000 or also called EUV NA, the new recording equipment / equipment that will allow us to move on because it will offer up to 0.55 NA lenses.
This should allow all your partners to create and burn simple patterns for up to 3nm patterns, until rumors that 2nm might be ready for a different build. The problem is that everything will be ready on the clock, the industry is getting stronger, TSMC, Samsung and Intel are trying to respond much faster and when it all comes true by 2023 they will be high and will have to turn to more patterns if EUV NA is not ready, to shoot the price again.
Masks and resistors, the final step of EUV NA
Each lithographic explosion (not LPP or similar) has meant a reduction in the specification of transistors at a rate of 0.7X per node, which reduces the price of each chip.
Starting at 20 nm, the choice was to leave the transistors light (called planes) and move to finFET and 3D technology to maintain the gain per chip and wafer ratio. This has increased the complexity of the complex, the numerical art has been prolonged, and until recently the industry has been blocked by patterns, scanners, and representatives.
These three ideas pose a constant challenge, since not only are the masks and patterns required, but they must be combined to give life to the IC by becoming successful.
Each step is given the name M after the number, where they are also recorded at different nanometers depending on the desired layer and the lenses used. Once the EUV limit has been reached at 5 nm, this will also be determined because it will be recorded at 30 nm in each mask to achieve the final aspect of the stated method.
The current problem is that adding masks or patterns is proving to create resistors and a larger lens means that the finFET transistors do not complete the recording properly, which makes the whole process, progressive on one side but worse on the other.
Therefore, EUV NA will need another type of new invoice transistor, to be named nanosheet FET, which should come next year if nothing happens. With it, 3nm is expected to collide with EUV NA and less by 2023 and from there the jump will be made at 2nm, reaching the visible atom limit soon.
Benefits of EUV NA
NA is a traditional recording of what is immersion in EUV, so it has a series of obvious benefits: a reduced fabric cycle, fewer errors in mask balances and greater design flexibility.
In addition, less complexity implies fewer steps in the process and therefore better performance for each user. As far as we know, the Zeiss company will manage to build Optics for ASML machines in EUV NA, so we will have to wait for them to solve the challenges, as it is currently a very complex and expensive process.
What seems clear is that if there is no delay, from 2023 we will face higher problems: reducing the size of transistors below the size of the atoms, something that has been researched for over a decade and all the predictions are overwhelmingly positive in their decision.
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