One of the challenges of three-dimensional integrated circuits or 3DICs lies in the type of interconnects used to vertically connect the different logic chips and / or memories to each other. The best-known method is the TSV, but the complications and the additional cost of its manufacture have led various foundries to develop alternative solutions, all based on so-called silicon bridges for interconnection. Until now, we were familiar with Intel’s EMIB technology and AMD’s X3D, the latter in conjunction with TSMC.
The latest to join is IBM, which has developed a silicon bridge that promises to lower production costs for future 3DIC designs, which they have dubbed DBHi.
Intel simplifies silicon bridges with DBHi technology
IBM has long stopped manufacturing chips, but it has not stopped researching the development of new technologies, such as the development of a 2nm node and now They surprise us with the development of their silicon bridge, which they named DBHi, acronyms that stand for direct-linked heterogeneous integration. Which consists of a silicon bridge to interconnect two chips vertically, without the need for TSV interconnects, located between the layers of vertically fabricated processors, for future CPUs, GPUs and APUs in 3DIC and 2.5DIC models.
The main difference between this and Intel EMIB technology is that the chips are glued to the laminate with standard C4 bumps and the bridge connects the chips or chiplets with micro bumps formed on either side of the silicon bridge. A design simpler than that of Intel and therefore easier to manufacture than this one. We don’t know at this time if a foundry will adopt this technology for future 2.5DIC and 3DIC configurations, since Intel and TSMC, the two larger ones have their own developed solutions.
The emergence of chips with 3DIC and 2.5DIC configurations has been seen as the solution to many Moore’s Law problems when it comes to evolving chip performance in the future. Its non-adoption is due to the high cost of manufacturing this type of integrated circuit using silicon channels. This has forced research and development in this area by the large foundries.
The future goes through silicon bridges
The bandwidth needed to interconnect future chips requires vertical interconnects, as this allows the number of interconnections to be increased. The advantage of this is that it allows the power consumption for the intercom to be reduced to tolerable levels. Something that would be quite achievable with classic serial connectivity.
We have boxes like Intel Foveros and EMIB, as well as future X3D technology from AMD. Which will be used by future processors for servers and data centers. However, we also cannot forget the development of new server processors based on architectures such as ARM and RISC-V, where the development of IBM’s licenses will give them a big push towards much more advanced designs.