The results are truly impressive for a single node jump and proof that Intel has been competing for real inferiority for many years due to the delays of its 10nm node, now called Intel 7. On the other hand, Intel 4 is a leap forward rather interesting, which calls the bet (late, yes) and which gradually puts the company back on the front of the stage.
Five nodes in 4 years, the bet starts with Intel 4
Intel 7 was brought to market more because of the investment the company made and the fact that investors had their eye on it than because of its actual performance. Admittedly, it was a leap forward, but at a huge cost in every way. The solution, first of all at least, is Intel 4 and… It’s very promising.
The improvements are very interesting and rarely can we say numbers like these:
- EUV Lithography first generation.
- Frequency jump at the same power of a 21.5%.
- At the same frequency, the power is reduced by 40%.
- Improved area scaling 2X.
All this against the current Intel 7 lithographic process, which was the densest compared to its predecessor… Until now. By breaking down point by point we will better understand what has been exposed.
First, EUV lithography was done using ASML scanners, which took Intel nearly two years to scale up to generate enough wafers per hour to secure enough chips. It consists of a fairly large number of layers, 18 in allwhich is shocking given that Intel 7 has 17. This is something we will also see with Intel 3 along the same lines, but at the moment there is no data.
The frequency jump is the most interesting, since neither TSMC nor Samsung with EUV have reached similar values and if we extrapolate it to the current Core 12, we would have frequencies of 6.6GHz
If Intel goes for efficiency, the result can be a low-end hit
And it is that Intel normally creates two libraries for each node: one of high density and another of high performance. In the case of Intel 4, this is going to cause some turn of events, as libraries for high density are apparently not available on this node, so only high performance remains as such.
That said, in high performance we can find, technically speaking, two approaches named above: expose the maximum available frequency, expose the node at its maximum efficiency. If Intel goes for both approaches by segmenting the range, we could end up with fast and, above all, very energy-efficient processors, which would be very interesting for gaming laptops and low-cost work computers, because if at 5.5 GHz they achieve a 40% reduction in consumption, one would speak of a Core i9-12900KS with barely 125 watts in full, figures that are now unthinkable.
| Intel 4 | Intel 7 | TSMC N5 | TSMC N3 | |
| HP Library Density | 160 MTr/mm^2 (estimated) | 80MTr/mm^2 | 130 MTr/mm^2 (estimated) | 208 MTr/mm^2 (estimated) |
| HD library density | None planned | 100MTr/mm^2 | 167 MTr/mm^2 (estimated) | 267 MTr/mm^2 (estimated) |
| Logical density | 2x | 2.7x | 1.83x | 1.6x |
| Perf (iso power) | 1.2X | 1.15x | 1.15x | 1.11x |
Improving area scaling is the technical calculation of all that has been said. And it is that the HP library (High Power) displays a density of 160MT/mm2 today (it could still be improved in a few million transistors, but not many), where the density increases up to 2X taking into account that Intel 7 was at 80 MT/mm2, with an iso performance of 1.2X.
Its direct rival is the TSMC N5 and to a lesser extent the Samsung N3 already with GAA
