In a conference that ha dado Intel in China, the president of the Centro de investigation que tiene la compañía en dicho país ha hablado de los objetivos que tienen de cara a 2030 y que se pueden en hacer chips cada vez más pequeños HP y que consuman each time less. Which translates to more transistors and more power efficiency. How do they plan to achieve this?
Moore’s Law, which was invented by the founder of Intel and also cannot be considered a law, but rather an observation, is often misinterpreted because the concepts about it are often confused. In any case, it should be specified that it is not a question of the economy of the chips or their power, but of the density of transistors in a given space which doubles from time to time. Although it has slowed down over time, the reality is that it is still valid today.
One trillion transistor chips by 2030 from Intel
For those of us who follow the evolution of the world of chips, that is to say semiconductors, it is very clear to us today that the future, in order to be able to double the density from time to time transistors, requires the use of new manufacturing and design techniques, in particular concepts such as split chips, and the use of three-dimensional structures, i.e. the stacking of chips on top of the others and all this to make chips that They will be up to 10 times more efficient and house up to a trillion transistors inside.
Currently the most complex chip used in PCs is NVIDIA’s AD102, which we believe is the core GPU in the RTX 4090, which has a density of 7.6% against this target, so we’re talking about a long enough time for Intel to achieve this goal, moreover, they have envisioned getting there by 2030, although we don’t know if they will do this in their Core processors or, conversely, in their GPU ARC. Let’s not forget that the so-called disintegrated microprocessors, or chiplets, make it possible to break the trellis limit of the wafer and to create compositions with a greater number of transistors than in a monolithic chip.
In any case, it must be borne in mind that once the single-block chips are shipped, the panorama will have completely changed, since this will mean the obvious use of smaller chips, which is also continued due to the increase in costs than each new chip manufacturing node.
An order of magnitude improvement in energy efficiency
If we are already talking about energy efficiency, what we must take into account is that these words, although it is a laudable goal for things like reducing the carbon footprint. We can not forget that we do not know the power with which they want to measure this parameter and the type of hardware, as well as the benchmarks they plan to use as a reference or failing today, parameters such as as the house of instructions per second, floating point power, etc.
This is a goal that will not be easy to achieve and will require the implementation of several technologies, many of which are still in development and others will soon be deployed. We’re talking about things like RibbonFET type transistors for densities of 2 nanometers or less, Power VIA power supplies, the use of advanced lithography systems that are currently unknown, and new chip packaging systems similar to Foveros.
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