PCIe 5.0 has not yet been released and the successor's guide has just been released. It is well known in the industry that currently the first bottle of new FPGAs, processors and RAM memory will be mentioned on the bus, so it is important to find a solution as a new version to continue to grow the market, both of which server as a utility.
PCI-SIG doesn't want to repeat problems with PCIe 4.0
The long process going on between PCIe 3.0 and PCIe 4.0 has involved numerous complaints from many sectors and companies to the Consortium for a number of years (7 specifically) from one version to another.
The industry is handling additional data, SSDs have reached almost the operating limit on their NVMe versions, graphics cards almost equalize all available buses and on FPGA servers require faster s torage and RAM connectivity.
The PCI-SIG Consortium had no choice but to increase the pace of research and development to alleviate the gaps that accumulated over the years, and consequently, in three years we will have two updates on bus use (if all goes well), because they intend to introduce this new version PCIe 6.0 sometime in 2021 .
5 steps to complete a reservation
As with any standard, it requires a series of steps before implementing the final model, in which companies can offer their own sand coins depending on their hardware requirements:
- Type 0.3: Bus concept and interface, description of key features and architecture.
- Type 0.5: initial draft, key features and comments from interested companies to add functionality.
- Version 0.7: A full-size draft, a complete description of all levels, including electricity, no more features.
- Version 0.9: the final framework to allow members to review their intellectual property expertise.
- Version 1.0: The final version is complete and official.
Features of PCIe 6.0
Currently and where there are no manufacturers or companies to add any features, the priority for this new version is the following:
- The bandwidth doubled to 64 GT / s from the 32 GT / s of PCIe 5.0.
- Pulse Amplitude Modulation 4PAM4), which will allow you to pack multiple pieces simultaneously on the serial port.
- It will be inclusive FEC (Forwarding Transmission Error) of low latency for processes that improve bandwidth efficiency.
- Compatibility with previous versions of PCIe is maintained
- Achieve the same with PCIe 5.0
In the meantime and the absence of all companies meeting at the next PCI-SIG Developers conference in 2020 to be held in early June there will be no more news. This is to be expected as well, since it is clearly intended to announce the deep immersion of technical features, so now it is all open.
