The development of the different processors does not happen overnight, as one begins to sell, the next is about to be mass-produced and the two-generation one with its design already completed. That’s why the Zen 5 rumors shouldn’t surprise us.
AMD adopts big.LITTLE in Zen 5
At least, that’s what rumors say about the fifth generation Zen, and it’s AMD Zen 5 will use a big little runtime and therefore, they will follow the same path that ARM cores years ago and Intel launched the Lakefield, but this will standardize massively to Alder Lake.
The big little execution that the AMD Zen 5 is supposed to adopt is based on using two different types of cores for the processor, which are fully compatible when running binary code but designed with two different performance metrics. Some are more focused on performance regardless of consumption, others would be more focused on consumption but at lower performance.
The makeup of each CCD will continue to be 8-core, with the corresponding IPC enhancements and optimizations made by AMD over the next two generations, but with each 8-core CCD, each accompanied by 4 additional less complex cores. Tall manufactured using TSMC’s 3nm process, which for the moment has not been used for the manufacture of any mass processor, not even in PostPC devices.
We already had clues about it
Specifically, an AMD patent that was released last year that talks about a big little core configuration like the one we’re talking about for the AMD Zen 5. The difference? They wouldn’t be cores in different clusters, but they would share access to the L1 cache, which is the most private of processors.
Thus, the operation of the big LITTLE in Zen 5 could therefore be different from the ARM cores and even from the Intel version and therefore the rumors about the AMD Zen 5 have been completely misinterpreted.
Go back to the monolithic model in Zen 5?
Another piece of information that has been said is that the AMD Zen 5 are going to be APUs, which would partly mean that AMD facing the Zen 5 will abandon the chiplet configuration that I adopt in Zen 2 and that everything indicates that we will see in Zen 4 It’s too early to tell, but one of the weaknesses of AMD’s Zen architectures is the latency due to the physical distance between the chipset and the IOD. Additionally, AMD is giving the Zen 2 and Zen 3 SoCs less L3 cache to give their chip-based desktop processors a little edge.
The other possibility is that it still relies on chiplets, but that the IOD fits inside an integrated GPU and its coprocessors, video codecs, display adapters, apart from the Northbridge and Southbridge. CPU. It is an idea that should not be dismissed and it would be entirely possible to do so.
In any case, the only thing that can be said is that it is still too early to speak specifically of Zen 5. All the more so when Zen 4 has not yet been presented and it is not There is no commercial chip that uses this node in its manufacture.
Leave a Reply