TSMC 3 nm, issues, features and dates of this period

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TSMC 3 nm, issues, features and dates of this period

Dates, features, issues, period, TSMC


A given chip has to face many problems when imported into a high-quality product. From heat to varying vibrations, to the frequencies it reaches, it all becomes increasingly complicated to work because reducing transistors and increasing population may require testing, measuring, and testing of each chip in a very complex way, that is, each lithograph adds some problems. .

5nm as a 7nm follower represents only some important changes

TSMC 3 nm

The biggest among them is that the transistor fin itself must be physically strong. Reducing each end size and gate requires a series of larger larger layers if standard FinFET transistors are maintained.

The twins and gates extend, becoming taller, so the number of materials and their placement is important to maintain the current flow uniform on the three walls of the said door. We can assume that by increasing the amplitude, it is likely to exceed the maximum current flow of each transistor, but the fact is that the ratio of diameter and height is key to increasing its efficiency, since the ratio is not proportional to the performance. .

This poses a control problem on the walls to ensure that the transistor controlling process is correct. To avoid this, artificial intelligence is used to machine learning to detect specific problems before a liar completes some important processes, so that it can be known in advance if it is a malicious failure.

The second problem facing 5nm is curiosity, since it is the transfer of data from the wafer and chip itself. Here again, Deep Learning takes the lead, because it can detect through machine vision images and through specific algorithms the problems and points of interest that developers have to focus on to perform the node production process.

This fact has created a timely shortening of the delivery of this 5 nm lithographic process, because thanks to deep readings TSMC has been able to detect and anticipate where the most serious problems were without having to spend huge hours based on evidence and critical recording errors.

3nm could be a paradigm shift for a new generation of places

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<p>If 5 nm forces the transistors to be stretched horizontally to separate them directly by larger values ​​and then by increasing the local thickness, 3 nm will represent the most important changes.</p>
<p>Although not approved by TSMC, NVIDIA and AMD may have to re-design their graphic designs, as Taiwan is more than going the Samsung route and replacing FinFET transistors with <strong>GAA or Gate-Round.</strong></p>
<p>The purpose of blocking is not this, as that would mean a major change, the beginning of blank masks and ending with a new type of recording and lenses. In addition, little is known that even though TSMC has been able to maintain FinFETs for one generation, new transistors will require new materials in diseases, such as cobalt or ruthenium.</p>
<p>As if that weren't enough, films and layers should be thin enough to prefer electric current, but this means it will be more difficult to clean them, fall off the polish, scale and, yes, test. As if that wasn't enough and they've been given another curious paradigm, which is the digital concept of a small chip in their transistors they get a bit more characteristic.</p>
<h3>Innovation and performance of each transistor</h3>
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<p>If we add this to new features that will define the wings and gates, we will find some of the latest problems, but they are multiplied depending on the difficulty in solving them. Power leaks, structural weaknesses, unstructured pressures and high misconduct will be some of the problems facing every company in the industry, not TSMC as small manufacturers.</p>
<p>Important details will be on the performance of each transistor. Long after the death of the transistor it stopped working, the same case when it was damaged. Currently this is not possible due to the same design and design: They will continue to operate, but with low performance which, when extended, reduces their setup to a low level.</p>
<p>Therefore, the efficiency of transistors is important to the industry and involves billions of dollars in research, prevention and detection, something that will be at 3 nm if you want to increase the efficiency of each chip. It's funny how the industry is changing. The hardness of the node is not so much to get the wafers working properly, but to make sure that the cutters get the functionality and the level of reliability that they are intended for and that they are designed for, the challenge is still there, because the thicker wafer doesn't work. chip if the final operation of this is less than its predecessor.</p>
<p>The next challenge will be atom as it is and from there the unbelievable field opens up where silicon may form the basis of a chain of particle computers that allows it to reduce its size under the atom, something truly amazing.</p>
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