Standardization of SSD is something that we will see in the following years, the reason is that many applications will start using these massive storage units, which have an impressive bandwidth. However, everything can be improved and that is why we are going to give you a quick overview of how NVMe memory access is evolving and how it will change the way PCs will be organized going forward in terms from memory.
Access NVMe memory from the processor today
To understand the current situation in the communication of the CPU with RAM and NVMe memory, we must take into account that although the virtual addressing of the CPU includes all the memory of the system in a unified way, in reality with regard to the physical access RAM and NVMe are not the same, because in order to access NVMe memory it is necessary to do it through the IOMMU as it is connected to the Southbridge I / O interface.
This means that in order to access data from an NVMe memory there are a lot of steps which if we want to copy the data as fast as possible from the NVMe chips from the SSD to the RAM involves high latency, despite the huge bandwidth. that PCI Express interfaces can provide.
Architects have long sought not only to unify memory space in addressing, but also memory access in order not only to reduce latency, but also to reduce the amount of internal cabling to move data. The main objective is to manufacture processors with less complex communications and less energy consumption.
Access to NVMe memory via CXL 2.0 in the future
The key to everything is in version 2.0 of the CXL protocol, which will bring all accelerators and I / O devices to common addressing with RAM, which means that the IOMMU will not be needed and opens the possibility that RAM and NVMe memory is accessible under the same CXL 2.0 interface.
The CPU would not directly access the NVMe chips, but the NVMe chips through the CXL 2.0 interface can directly copy the data to the system RAM directly without having to go through the IOMMU and all the address conversion work.
This step is important for the adoption of perpetual RAMs such as MRAM, which maintain their contents even after the loss of electrical load and which combine the persistent storage of NAND Flash with the speed of RAM.
Obviously, for this, new communication interfaces will have to be created for both RAM and NVMe memory, the reason is that the power consumption of the PCIe port is too high against the memory bandwidths, which is why a future DDR6 or DDR7 memory compatible with a CXL 2.0 interface cannot be excluded.
Pre-unify RAM and NVMe before persistent memory?
We also cannot forget the existence of memories which, while not being persistent memories, include both NVMe and LPDDR memory in the same package, of course these memories are not designed to use the memory. ‘CXL 2.0 interface, but since the manufacturers of memory and NVMe RAM are the same, so we should not be surprised to see in the future DIMMs, SO-DIMMs or memory soldered on the board integrating into the both RAM and NVMe in the same package.
It should be taken into account that one of the most common design issues is space, integrating RAM and NVMe memory in the same space results in space reduction and in systems more compact, obviously the fact of unifying the two types of memory under the same packaging opens the possibility that the two share the same communication interface, which, given the evolution of the things, will be CXL 2.0, since it is is a common standard on which all manufacturers agree.
