On the PC, various interfaces communicate with each other with the CPU, APU or GPU. But what is the part that unifies the various signals that go in and out of a processor? We explain what this common piece is in all hardware and how it works. What is commonly referred to as SerDes.
What is a SerDes?
The SerDes have their origin in the world of telecommunications. The reason for its existence is quite simple, sending data through a single cable instead of several at the same time reduces the complexity of the internal intercom of a telecommunications network. Now, if we think about it, the way the various logical and memory parts of a processor and a system are communicated is done through a series of cables.
At first glance, in terms of performance, it might seem like using a parallel interface is always much better, but there are a number of factors that make serial interfaces better. What are? First of all, parallel interfaces take up much more space and are more sensitive to electromagnetic waves, in addition to consuming more at the same clock speed. The downside of serial interfaces is that they have a higher latency in sending data.
However, in a hardware design there are parts with a serial interface and others with a parallel interface. How to connect them to each other their communication interfaces are different? Well, with a SerDes, the main job of which is to communicate various elements, including peripherals, with the CPU.
All roads lead to Rome
Take a look at your PC and the various interfaces for internal components and external devices. We have interfaces like SATA, PCI Express, USB and many more. Each of them has interfaces for different types of devices. Well, internally each of these interfaces doesn’t connect directly to the mainframe hub, but rather to a series of SerDES.
Not surprisingly, there are different input and output interfaces for devices of all kinds that are designed to interact with the standard specifications of different SerDes. What are these interfaces? Well, we have the case of PCI Express interfaces in their different technologies, for storage like SATA and SAS, for video transmission like DisplayPort and HDMI, for networks like different gigabit ethernet interfaces, etc. But, the thing is not just limited to the I / O interfaces for peripherals and components, but it goes further and the RAM memory also communicates via a SERDES with the central hub that each processor has, called Northbridge and which is in charge of communicating the different elements between them and each of them with the RAM memory.
Therefore, the different interfaces not only in design, but also in evolution, must take into account the evolution of SerDes at this precise moment, since these interfaces will be connected to these in the internal logic of each circuit. integrated. It must be taken into account that internally in a processor if there are too many interconnections then the complexity of the intercommunication will be too great. It is therefore preferable to reduce the number of interconnects by serializing the incoming data in exchange for an increase in the clock speed.
How does a SerDes work?
If we take this straightforward definition into account, then a SerDes is still a piece of hardware made up of a multiplexer and a demultiplexer, which are two basic types of combinatorial systems. What a multiplexer or MUX does is convert a single signal into several different signals and a demultiplexer or DEMUX does the opposite task.
The difference is that the SerDES takes clock speed into account, because depending on when the data is transmitted, the interpretation by the processor is one or the other. In other words, when a request for data is made from any component of a hardware system, there are times and therefore a window of opportunity to transmit the data. How does this translate? Well, the data is transmitted on a time basis so it involves a clock signal.
Suppose we want to serialize a parallel signal that is transmitted through a series of Full Duplex lines, which transmit 1 bit of information in each direction. The bandwidth is 1.25 Gbps, so that means each line is operating at 625 MHz. We have four lines in total, so if we serialize the signal we’ll be talking about a 5Gbps signal, which in the case of a Full Duplex required the serial interface to operate at 2.5GHz. The reverse path is therefore easy to understand, we can run the 5 Gbps signal over two lines using a speed of 1.25 GHz for each line, over four lines using a clock speed of 625 MHz each, and and so on.
The evolution of SerDes
Before commenting on how SerDES completely influences the design of future input and output interfaces, which implies that the development of future interfaces or changes to existing interfaces depends entirely on the SerDes to which they are connected, since they must be able to communicate with them. For example, SerDES at 112 Gbps, the fastest on the market today, uses PAM4 signaling, so this type of signaling sounds for interfaces like the future PCI Express 6.0.
However, advancing the communication speed of SerDes is not an easy task, with each new generation in which the communication bandwidth is increased, new challenges appear, especially with the elements that degrade the quality of the signal used. We also cannot forget that the voltage does not change in the same way as the clock speed, which causes the power consumption of the interfaces to skyrocket. Hence the adoption of PAM4 interfaces to avoid increasing the clock speed to limits that would not be acceptable.
At the moment, only the GDDR6X memory of NVIDIA RTX 30 uses the PAM4 interface, which means that the internal SerDes of these GPUs use this type of interface to communicate with the GPU. This influences the rest of the I / O interfaces of these GPUs. At the same time, it complicates the adoption of a PAM4 system in other systems, because it means that the interfaces must adapt to the time rules of the SerDes included in the processor.