Facing the sixth generation of the PCI Express interface, we are going to see a series of important changes in order to be able to continue the tradition to which we are accustomed. Which says that each new PCIe gene doubles its bandwidth and therefore the amount of data that can be transmitted end-to-end. However, in the case of PCI Express 6.0, profound changes were necessary in the development of the sixth generation of this interface.
PCI Express 6.0 General Specifications
The first thing that interests us about PCI Express 6.0 is how much information we can transmit per second through this interface. Let’s not forget that on the motherboards of our PCs we can find interfaces with 1, 4, 8 and up to 16 different lines, where the data is sent in parallel on each one. The total bandwidth? 256 GB/s in both directions for the interface used in graphics cards and 64 GB/s for that of M.2 SSDs. Of course, we must keep in mind that we are talking about the added bandwidth in both directions, that is, taking into account reading and writing at the same time.
The PCI Express interface has always been backward compatible with previous versions of the protocol, this means we can plug a PCI Express 1.0 card into a PCI Express 6.0 slot and it will work as the pinout will be exactly the same. This is a double-edged sword, because to increase bandwidth, additional pins cannot be placed, and therefore the clock speed at which the interface operates must be increased. That is, the data pumps per second to transmit the data.
The problem with PCI Express 6.0? As we increase the clock speed of an interface it becomes more unstable with distance and after six generations they had to make changes to the interface due to the high speed at which the interface works traditionally. The problem comes when it is necessary to transmit 256 Gb/s on a Full Duplex interface. Allowing 1 bit for each direction to be transmitted simultaneously requires the interface speed to increase to 128 GHz and at these speeds signal integrity is seriously compromised.
This forced a series of measures to be taken to make the switch to PCI Express 6.0 possible, starting with encryption.
PCI Express 6.0 and PAM4 encoding
How does an external or internal interface on a chip know if the value is a 1 or a 0? Well simple, depending on the voltage in which the information is transmitted. Binary systems are based on the use of two voltages with sufficient distance between them so that the voltage drop or rise does not cause signal confusion. In analog systems, a simple variation of voltage implies a change of information. This is why computers speak in binary.
What does this have to do with PCI Express 6.0? As we cannot increase the bandwidth because the signal is distorted and neither can the number of pins because of backward compatibility, a solution must be sought and this requires the use of PAM4 or Pulse Amplitude Modulation encoding, which we have already seen in GDDR6X and is not based on using two voltage values but 4 voltage values for each pin. This way we can encode the values 00, 01, 10 and 11 on each pin. Four values in total, instead of the two classic values which would be 0 or 1.
The solution avoids increasing bandwidth and pins, but tells us that in PCI Express 7.0 this will no longer be possible from conventional methods. We can see the use of photonics and optical interfaces, but with PCI Express 6.0 improvements fresh out of the oven, better be patient with its successor.
Changes in the package system
The move to PAM-4 changed the way the PCI Express 6.0 interface sends its packets, although it is backwards compatible with previous generations by communicating in traditional PAM-2 or NRZ mode. The reality is that the PAM-4 format does not support the old packet system and hence the communication protocol has changed due to this.
Forward Error Correction
The first change was the so-called Forward Error Correction or FEC, which is the new protocol for correcting errors in sending data. The problem is that the bandwidth to process is so high that the FEC adds huge latency to sending the data. To mitigate this in the PCI Express 6.0 standard, a packet type called FLIT is used. A packet is nothing more than a set of bits with a specific destination. The sending latency of each FLIT? It depends on the number of lanes on the interface, but each packet has a latency of only 2 ns on a 16 lane PCI Express 6.0, but it goes up to 32 ns on a single lane interface.
FEC only works with fixed sizes, which is why FLIT has a size of 256 bytes per send. Each packet or TLP can have a size ranging from 0 bytes to 4096 bytes and therefore each packet can consist of multiple FLITS.
Cyclic redundancy check
Cyclic redundant verification is a code error correction system commonly used in storage drives and digital networks that has been incorporated into the PCI Express 6.0 standard to verify that data transmitted end-to-end maintains its integrity and that ‘no bits were changed in the process.
This is achieved with a series of polynomial calculations carried out by a series of specialized units for this which are going to be included with the interface. It’s something that makes sense with the huge amount of data that’s going to be transmitted and it’s a saving in the case of future M.2 SSD manufacturers who won’t have to add this feature in their SSDs the same time. times already come as standard the CRC on the interface.
New Low Power Mode in PCI Express 6.0
PCI Express 6.0 adds a new low power state called L0P. This mode allows the interface to reduce its energy consumption when the transmitted data flow is less than what the interface can transmit. It does this by varying the clock speed at which it operates for the specific times when the data to be transmitted is at a lower volume.
This mechanism is closely related to the new technologies introduced in the sixth version of PCIe 6, so it can only be used with devices compatible with this generation of interface.