Rocket Lake is actually nothing more than a lake of ice, but with the main difference that Intel designed it so that it can be manufactured under its 14nm node, which is surprising, because the fact of ‘using one node or another is not something simple and requires the complete overhaul of the whole chip, as well as some optimizations because, unlike the usual stage in which a version with a more advanced node is conceived, in this case, Intel moved to a less advanced node.
The paradox is that we are facing the first major change in years if we are talking about Intel architectures for desktops, since the changes at the IPC level from the sixth generation with Skylake to the tenth with Comet Lake have been zero, the reason is that Intel spent four years using the same core and releasing versions of the same processor with minor improvements.
All of this while they polished their already veteran 14nm node, hoping that the 10nm node would have enough performance in production to make the jump. Due to these issues, Intel made the decision to make a 14nm version of its Ice Lake in order to cope with Intel Core Gen 11 and as before Alder Lake.
La Arquitectura General del Intel Rocket Lake-S
Rocket-Lake S is an 8-core processor with Hyperthreading capability, these are based on Intel’s Cypress Cove architecture, which is a 14nm port of Ice Lake’s Sunny Cove.
On the other hand, where if there are changes in the part of the integrated GPU which is now an Intel Xe LP of 32 execution units, equivalent to an AMD GPU of 4 processing units, so in the graphics section its iGPU only respects this minimum minimum. The really remarkable thing? Having a hardware video CODEC for AV1, so the CPU will not suffer while playing these videos.
When it comes to I / O, Intel decided to place a 20-rail PCIe interface, which means the most common configuration we are going to see is the dedicated graphics card with an SSD drive, the problem is that the CPU does not. integrate other I / O interfaces inside, as it uses Intel’s Z590 chipset.
Chipset Z590, the Rocket Lake-S companion
If there is something good about Intel processors, it is the use of the Direct Media interface, an interface to communicate the Northbridge built into the processor with the Southbridge of the same. At AMD, they use PCI Express lanes for this, so we can say that the 24 lanes of AMD processors via IO Hub, are equivalent to the 20 PCIe lanes of the Intel Rocket Lake-S + 8 via DMI.
The downside is that unlike AMD where the Southbridge integrated into the CPU provides a USB controller, here the Z590 chipset is needed, which is done on purpose by Intel to sell the Z590. The chipset supports up to 3 20 Gb / s USB 3.2 2.2 ports, 10 USB 3.2 Gen 2 × 1 10 Gb / s ports, 10 USB 3.2 Gen 2 × 1 5 Gb / s ports and up to 14 USB ports 2.0.
If we talk about other I / O ports, it supports up to 6 SATA 6 Gb / s ports for conventional hard drives which can be placed in a RAND 1.5, 10 configuration. Built-in LAN for Ethernet cable network connection, built-in WiFi with WiFi support and 6 24 PCI Express 3.0 lanes.
Cypress Cove, the heart of Rocket Lake-S based in Sunny Cove
The Cypress Cove core drives the first IPC jump of Intel desktop processors since Skylake, so performance comparing core to core at the same speed is better than the previous generation.
As this is a 14nm port of Sunny Cove, it is not a new architecture, it is more, it was showcased at the Intel Architecture Days in 2018, so the architecture on the launch date of Rocket Lake-S is over two years old.
It is surprising that Intel did not decide to launch a Tiger Lake for desktop, since the core of Willow Cove of these has a performance between 10% and 20% at the same clock speed and better. consumption than the Sunny Cove / Cypress Cove. This disparity in Intel Gen 11 makes us think that Rocket Lake-S is a side project to Tiger Lake and it was much more expensive for Intel to cancel the project than to continue running it.
Specifications of Cypress Cove / Sunny Cove Core
Intel didn’t give specific details on Cypress Cove beyond the fact that it is the 14nm version of the Sunny Cove that they presented over two years ago, in any case here is a list of its technical characteristics:
- First, its CPI rose, averaging 19% in some benchmarks compared to Skylake-based cores.
- The micro-cache for micro-instructions which is 50% larger, going from 1536 entries to 2.25k entries.
- The IDQ has also been improved from 70 MicroOps per second compared to 64 of previous generations.
- The processor pre-readers used during the instruction fetch phase, as well as the jump prediction unit used to pre-analyze the code and find conditional jumps have been improved.
- Regarding the part dedicated to decoding instructions, the paths are now 20% wider, so there is less contention, the scheduler of the instructions in charge of scheduling the sending to the execution units of the CPU from 97 to 160 entries. And sending instructions to threads from the Dispatch unit increased from 8 to 10.
- The virtual address generation unit, AGU, has also been improved.
- As for the cache, the first level data cache has increased from 32KB to 48KB, while the L2 cache is 512KB.
- In Cypress Cove, the top level cache is L3 per core which is 2MB or a total of 16MB for the 8 core configuration.
As you can see, the Rocket Lake core architecture is a big change from the 6th to 10th Gen Intel Cores, in terms of performance per core, despite not having a 10-core configuration wasted in multicore performance against Comet Lake with this configuration,
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